Omron CP1H-CPU - 05-2006, Руководство по эксплуатации

Страница: 194 / 669

163
Timers and Counters
Section 4-13
4. The present value of TIM, TIMX(550), TIMH(015), TIMHX(551), TM-
HH(540), TMHHX(552), TIMW(813), TIMWX(816), TMHW(815) and TMH-
WX(817) timers programmed with timer numbers 0000 to 2047 will be
updated even when jumped between JMP and JME instructions or when
in a task that is on standby. The present value of timers programmed with
timer numbers 2048 to 4095 will be held when jumped or when in a task
that is on standby.
Forcing Bit Status Timer Completion Flags can be force-set and force-reset.
Timer PVs cannot be force-set or force-reset, although the PVs can be
refreshed indirectly by force-setting/resetting the Completion Flag.
Restrictions There are no restrictions in the order of using timer numbers or in the number
of N.C. or N.O. conditions that can be programmed. Timer PVs can be read as
word data and used in programming.
4-13-2 Counter Area (C)
The 4,096 counter numbers (C0000 to C4095) are shared by the CNT,
CNTX(546), CNTR(012), CNTRX(548), CNTW(814), and CNTWX(818)
instructions. Counter Completion Flags and present values (PVs) for these
instructions are accessed with the counter numbers.
When a counter number is used in an operand that requires bit data, the
counter number accesses the Completion Flag of the counter. When a
counter number is used in an operand that requires word data, the counter
number accesses the PV of the counter.
The refresh method for counter PVs can be set from the CX-Programmer to
either BCD or binary. (Refer to the previous page).
It is not recommended to use the same counter number in two counter
instructions because the counters will not operate correctly if they are count-
ing simultaneously. If two or more counter instructions use the same counter
number, an error will be generated during the program check, but the counters
will operate as long as the instructions are not executed in the same cycle.
The following table shows when counter PVs and Completion Flags will be
reset.
Forcing Bit Status Counter Completion Flags can be force-set and force-reset.
Counter PVs cannot be force-set or force-reset, although the PVs can be
refreshed indirectly by force-setting/resetting the Completion Flag.
Restrictions There are no restrictions in the order of using counter numbers or in the num-
ber of N.C. or N.O. conditions that can be programmed. Counter PVs can be
read as word data and used in programming.
Instruction name Effect on PV and Completion Flag
Reset Mode
change
PLC startup Reset Input CNR(545)/CN
RX(547)
Interlocks
(IL-ILC)
COUNTER:
CNT/CNTX(546) PV
→
0
Flag
→
OFF
Maintained Maintained Reset Reset Maintained
REVERSIBLE
COUNTER:
CNTR(012)/CNTRX(548)
COUNTER WAIT:
CNTW(814)/CNTWX(818)