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Memory Cassette Functions
Section 6-5
• For XA CPU Units, the built-in analog output control is temporarily
stopped while a Memory Cassette data transfer or verification is in
progress. Therefore, if the IOM Hold Bit (A500.12) is ON and the exter-
nally transmitted analog output value is being held when the operating
mode is switched from RUN or MONITOR to PROGRAM and a Memory
Cassette data transfer or verification is executed, the analog output value
cannot be held during the transfer or verification and the value will be
changed. When the transfer or verification has been completed, the ana-
log output value will revert to the originally held value.
• The following table shows whether data transfers are enabled when the
CPU Unit is protected in various ways.
6-5-5
Procedure for Automatic Transfer from the Memory Cassette at
Startup
Use the following procedure to enable automatic transfer at startup.
1,2,3...
1.
Prepare a Memory Cassette with the required data stored.
2.
With the power supply turned OFF to the CPU Unit, remove the cover from
the Memory Cassette slot and insert the Memory Cassette.
3.
Open the cover for the CPU Unit's PERIPHERAL section and set DIP
switch pin SW2 to ON.
4.
Turn ON the power supply to the CPU Unit.
5.
The automatic transfer from the Memory Cassette will begin, and the
progress of the transfer will be displayed at the 7-segment LED indicator.
6.
After the automatic transfer has been completed, turn OFF the power sup-
ply to the CPU Unit.
Type of protection
Transfer from CPU Unit
to Memory Cassette
Transfer from Memory
Cassette to CPU Unit
Not protected.
Yes
Yes
System protected by DIP switch
pin SW1 set to ON.
Yes
No
Protected by password. Over-
writing and duplication both per-
mitted.
Yes
Yes
Protected by password. Over-
writing prohibited and duplica-
tion permitted.
Yes
Transfer enabled only at
startup.
Protected by password. Over-
writing permitted and duplica-
tion prohibited.
No
Yes
Protected by password. Over-
writing and duplication both pro-
hibited.
No
Transfer enabled only at
startup.
MEMORY
1 2 3 4
5 6
ON
DIP switch pin
SW2 set to ON.
Содержание CP1H-CPU - 05-2006
Страница 1: ...OPERATION MANUAL CP1H CPU Unit SYSMAC CP Series CP1H X40D CP1H XA40D CP1H Y20DT D Cat No W450 E1 02...
Страница 2: ...CP1H X40D CP1H XA40D CP1H Y20DT D CP1H CPU Unit Operation Manual Revised May 2006...
Страница 3: ...iv...
Страница 11: ...xii TABLE OF CONTENTS...
Страница 15: ...xvi...
Страница 19: ...xx...
Страница 31: ...xxxii Conformance to EC Directives 6...
Страница 71: ...40 Function Blocks Section 1 5...
Страница 133: ...102 Computing the Cycle Time Section 2 7...
Страница 169: ...138 CPM1A Expansion I O Unit Wiring Section 3 6...
Страница 411: ...380 Clock Section 6 8...
Страница 519: ...488 Replacing User serviceable Parts Section 10 2...
Страница 527: ...496 Standard Models Appendix A...
Страница 535: ...504 Dimensions Diagrams Appendix B...
Страница 628: ...597 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Страница 629: ...598 Connections to Serial Communications Option Boards Appendix F...
Страница 659: ...628 PLC Setup Appendix G...
Страница 665: ...634 Index work words 159 write protection 370...
Страница 667: ...636 Revision History...