151
I/O Area and I/O Allocations
Section 4-2
Words are allocated to each model of Unit as described below.
m: The last input word allocated to the CPU Unit, Expansion I/O Unit, or
Expansion Unit on the left of the Unit being described
n:
The last output word allocated to the CPU Unit, Expansion I/O Unit, or
Expansion Unit on the left of the Unit being described
Expansion I/O Units
Models with 40 I/O Points (CPM1A-40EDR/40EDT/40EDT1)
Twenty-four input bits in two words are allocated (bits 00 to 11 in word m+1
and bits 00 to 11 word m+2). Sixteen output bits in two words are allocated
(bits 00 to 07 in word n+1 and bits 00 to 07 in word n+2).
Two input words (24 bits) and two output words (16 bits) are allocated to a 40-
point Expansion I/O Unit, just as for X and XA CPU Units. Input bits 12 to 15
are always cleared and cannot be used as work bits. Output bits 08 to 15,
however, can be used as work bits.
Models with 20 I/O Points (CPM1A-20EDR1/20EDT/20EDT1)
Twelve input bits are allocated in one word (bits 00 to 11 in word m+1). Eight
output bits are allocated in one word (bits 00 to 07 in word n+1).
One input word (12 bits) and one output word (8 bits) are allocated for 20-
point Expansion Unit.
Input bits 12 to 15 are always cleared by the system and cannot be used as
work bits. Output bits 08 to 15, however, can be used as work bits.
Model with 8 I/O Points (CPM1A-8ED)
Eight input bits are allocated in one word (bits 00 to 07 in word m+1). There
are no output bits allocated.
Only one word (8 bits) is allocated to 8-input Expansion I/O Units. No output
words are allocated. Input bits 08 to 15 are always cleared by the system and
cannot be used as work bits.
Eight-output Models (CPM1A-8ER/8ET/8ET1)
There are no input bits (no words are allocated).
Eight output bits are allocated in one word (bits 00 to 07 in word n+1).
Only one word (8 bits) is allocated to 8-output Expansion I/O Units. No input
words are allocated. Output bits 08 to 15 can be used as work bits.
15 14
13 12
11 10
09 08
07 06
05 04 03 02 01
00
m+1
m+2
Do not use.
n+1
n+2
Can be used as work bits.
Input
bits
Output
bits
15 14
13 12
11 10
09 08 07
06
05 04 03 02 01 00
n+1
Do not use.
Can be used as work bits.
Output bits
Input bits
m+1
15 14 13 12
11 10 09
08 07
06
05
04 03 02 01 00
m+1
Do not use.
Input
bits
15 14 13 12
11 10 09 08 07
06
05
04 03 02 01 00
n+1
Can be used as work bits.
Outputs
Содержание CP1H-CPU - 05-2006
Страница 1: ...OPERATION MANUAL CP1H CPU Unit SYSMAC CP Series CP1H X40D CP1H XA40D CP1H Y20DT D Cat No W450 E1 02...
Страница 2: ...CP1H X40D CP1H XA40D CP1H Y20DT D CP1H CPU Unit Operation Manual Revised May 2006...
Страница 3: ...iv...
Страница 11: ...xii TABLE OF CONTENTS...
Страница 15: ...xvi...
Страница 19: ...xx...
Страница 31: ...xxxii Conformance to EC Directives 6...
Страница 71: ...40 Function Blocks Section 1 5...
Страница 133: ...102 Computing the Cycle Time Section 2 7...
Страница 169: ...138 CPM1A Expansion I O Unit Wiring Section 3 6...
Страница 411: ...380 Clock Section 6 8...
Страница 519: ...488 Replacing User serviceable Parts Section 10 2...
Страница 527: ...496 Standard Models Appendix A...
Страница 535: ...504 Dimensions Diagrams Appendix B...
Страница 628: ...597 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Страница 629: ...598 Connections to Serial Communications Option Boards Appendix F...
Страница 659: ...628 PLC Setup Appendix G...
Страница 665: ...634 Index work words 159 write protection 370...
Страница 667: ...636 Revision History...