![background image](http://html1.mh-extra.com/html/omron/cp1h-cpu-05-2006/cp1h-cpu-05-2006_operation-manual_742082200.webp)
169
Index Registers
Section 4-15
tions shown in the following table. Use these instructions to operate on the
Index Registers as pointers.
The Index Registers cannot be directly addressed in any other instructions,
although they can usually be used for indirect addressing.
The SRCH(181), MAX(182), and MIN(183) instructions can output the PLC
memory address of the word with the desired value (search value, maximum,
or minimum) to IR0. In this case, IR0 can be used in later instructions to
access the contents of that word.
4-15-1 Using Index Registers
Processing of multiple (identical) instructions such as consecutive addresses
for table data can be merged into one instruction by combining repetitive pro-
cessing (e.g., FOR(513) and NEXT(514)instructions) with indirect addressing
using Index Registers, thereby simplifying programming.
The Index operation uses the following procedure.
1.
PLC memory addresses for the addresses in the Index Registers are
stored using a MOVR instruction.
2.
Operation is then executed by indirectly addressing Index Registers to the
operand for Instruction A.
3.
The addresses are moved using processing such as adding, subtracting,
incrementing, or decrementing the Index Register (see note).
Instruction group
Instruction name
Mnemonic
Data Movement
Instructions
MOVE TO REGISTER
MOVR(560)
MOVE TIMER/COUNTER PV TO REG-
ISTER
MOVRW(561)
DOUBLE MOVE
MOVL(498)
DOUBLE DATA EXCHANGE
XCGL(562)
Table Data Processing
Instructions
SET RECORD LOCATION
SETR(635)
GET RECORD NUMBER
GETR(636)
Increment/Decrement
Instructions
DOUBLE INCREMENT BINARY
++L(591)
DOUBLE DECREMENT BINARY
– –L(593)
Comparison Instructions
DOUBLE EQUAL
=L(301)
DOUBLE NOT EQUAL
< >
L(306)
DOUBLE LESS THAN
<
L(311)
DOUBLE LESS THAN OR EQUAL
<
=L(316)
DOUBLE GREATER THAN
>
L(321)
DOUBLE GREATER THAN OR EQUAL
>
=L(326)
DOUBLE COMPARE
CMPL(060)
Symbol Math Instructions DOUBLE SIGNED BINARY ADD WITH-
OUT CARRY
+L(401)
DOUBLE SIGNED BINARY SUBTRACT
WITHOUT CARRY
–L(411)
IR0
,IR0
Instruction execution
repeatedly incrementing
IR0 by 1
Instruction
Indirect
addressing
Table data
Содержание CP1H-CPU - 05-2006
Страница 1: ...OPERATION MANUAL CP1H CPU Unit SYSMAC CP Series CP1H X40D CP1H XA40D CP1H Y20DT D Cat No W450 E1 02...
Страница 2: ...CP1H X40D CP1H XA40D CP1H Y20DT D CP1H CPU Unit Operation Manual Revised May 2006...
Страница 3: ...iv...
Страница 11: ...xii TABLE OF CONTENTS...
Страница 15: ...xvi...
Страница 19: ...xx...
Страница 31: ...xxxii Conformance to EC Directives 6...
Страница 71: ...40 Function Blocks Section 1 5...
Страница 133: ...102 Computing the Cycle Time Section 2 7...
Страница 169: ...138 CPM1A Expansion I O Unit Wiring Section 3 6...
Страница 411: ...380 Clock Section 6 8...
Страница 519: ...488 Replacing User serviceable Parts Section 10 2...
Страница 527: ...496 Standard Models Appendix A...
Страница 535: ...504 Dimensions Diagrams Appendix B...
Страница 628: ...597 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Страница 629: ...598 Connections to Serial Communications Option Boards Appendix F...
Страница 659: ...628 PLC Setup Appendix G...
Страница 665: ...634 Index work words 159 write protection 370...
Страница 667: ...636 Revision History...