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167
Index Registers
Section 4-15
With the offset and increment/decrement variations, the Index Registers can
be set to base values with MOVR(560) or MOVRW(561) and then modified as
pointers in each instruction.
Note It is possible to specify regions outside of I/O memory and generate an Illegal
Access Error when indirectly addressing memory with Index Registers. Refer
to Appendix E Memory Map for details on the limits of PLC memory
addresses.
The following table shows the variations available when indirectly addressing
I/O memory with Index Registers. (IR
@
represents an Index Register from IR0
to IR15.)
Example
This example shows how to store the PLC memory address of a word (CIO 2)
in an Index Register (IR0), use the Index Register in an instruction, and use
the auto-increment variation.
MOVR(560)
2
IR0
Stores the PLC memory address of
CIO 2 in IR0.
MOV(021)
#0001
,IR0
Writes #0001 to the PLC memory ad-
dress contained in IR0.
MOV(021)
#0020
+1,IR0 Reads the content of IR0, adds 1,
and writes #0020 to that PLC memo-
ry address.
I/O Memory
Pointer
Set to a base value
with MOVR(560) or
MOVRW(561).
Variation
Function
Syntax
Example
Indirect addressing
The content of IR
@
is treated as
the PLC memory address of a bit
or word.
,IR
@
LD ,IR0
Loads the bit at the PLC
memory address contained
in IR0.
Indirect addressing
with constant offset
The constant prefix is added to the
content of IR
@
and the result is
treated as the PLC memory
address of a bit or word.
The constant may be any integer
from –2,048 to 2,047.
Constant ,IR
@
(Include a + or –
in the constant.)
LD +5,IR0
Adds 5 to the contents of IR0
and loads the bit at that PLC
memory address.
Indirect addressing
with DR offset
The content of the Data Register
is added to the content of IR
@
and
the result is treated as the PLC
memory address of a bit or word.
DR
@
,IR
@
LD
DR0,IR0
Adds the contents of DR0 to
the contents of IR0 and
loads the bit at that PLC
memory address.
Indirect addressing
with auto-increment
After referencing the content of
IR
@
as the PLC memory address
of a bit or word, the content is
incremented by 1 or 2.
Increment by 1:
,IR
@
+
Increment by 2:
,IR
@
++
LD , IR0++
Loads the bit at the PLC
memory address contained
in IR0 and then increments
the content of IR0 by 2.
Indirect addressing
with auto-decrement
The content of IR
@
is decre-
mented by 1 or 2 and the result is
treated as the PLC memory
address of a bit or word.
Decrement by 1:
,–IR
@
Decrement by 2:
,– –IR
@
LD , – –IR0 Decrements the content of
IR0 by 2 and then loads the
bit at that PLC memory
address.
Содержание CP1H-CPU - 05-2006
Страница 1: ...OPERATION MANUAL CP1H CPU Unit SYSMAC CP Series CP1H X40D CP1H XA40D CP1H Y20DT D Cat No W450 E1 02...
Страница 2: ...CP1H X40D CP1H XA40D CP1H Y20DT D CP1H CPU Unit Operation Manual Revised May 2006...
Страница 3: ...iv...
Страница 11: ...xii TABLE OF CONTENTS...
Страница 15: ...xvi...
Страница 19: ...xx...
Страница 31: ...xxxii Conformance to EC Directives 6...
Страница 71: ...40 Function Blocks Section 1 5...
Страница 133: ...102 Computing the Cycle Time Section 2 7...
Страница 169: ...138 CPM1A Expansion I O Unit Wiring Section 3 6...
Страница 411: ...380 Clock Section 6 8...
Страница 519: ...488 Replacing User serviceable Parts Section 10 2...
Страница 527: ...496 Standard Models Appendix A...
Страница 535: ...504 Dimensions Diagrams Appendix B...
Страница 628: ...597 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Страница 629: ...598 Connections to Serial Communications Option Boards Appendix F...
Страница 659: ...628 PLC Setup Appendix G...
Страница 665: ...634 Index work words 159 write protection 370...
Страница 667: ...636 Revision History...