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190
Interrupt Functions
Section 5-1
Procedure
Note
The input interrupt (counter mode) function is one of the input interrupt func-
tions and executes an interrupt based on the pulse count. If the input pulse
frequency is too high, interrupts will occur too frequently and prevent normal
cyclic task processing. In this case, cycle time too long errors may occur or
the pulse input may not be read.
The maximum total frequency of the counter-mode interrupt inputs is 5 kHz.
Even in this case, the high frequencies may adversely affect other devices’
operation or the system load, so check the system’s operation thoroughly
before using the counters at high frequencies.
PLC Setup
The procedures for using the CX-Programmer to set the PLC Setup are the
same as the procedures for input interrupts (direct mode). Refer to 5-1-2 Input
Interrupts (Direct Mode) for details.
Writing the Ladder
Program
MSKS(690) Settings
The MSKS(690) instruction must be executed in order to use input interrupts.
The settings made with MSKS(690) are enabled with just one execution, so in
general execute MSKS(690) in just one cycle using an up-differentiated condi-
tion.
MSKS(690) has the following two functions and three of the instructions are
used in combination. If up-differentiated input pulses are being used, the first
MSKS(690) instruction can be omitted since the input is set for up-differentia-
tion by default.
Select the input interrupts (counter
mode).
• Determine the inputs to be used for input
interrupts and corresponding task numbers.
↓
Wire the inputs.
• Wire the inputs.
↓
Set the PLC Setup.
• Use the CX-Programmer to select the inter-
rupt inputs in the PLC Setup.
↓
Set the counter SVs.
• Set the interrupt counter SVs in the corre-
sponding AR Area words.
↓
Write the ladder program.
• Write the programs for the corresponding
interrupt task numbers.
• Use MSKS(690) to specify up-differentiation
or down-differentiation.
• Use MSKS(690) to enable input interrupts (in
counter mode).
@MSKS(690)
N
S
@MSKS(690)
N
S
Execution condition
2. Enables or disables the input interrupt.
1. Specifies up-differentiated or
down-differentiated inputs.
Содержание CP1H-CPU - 05-2006
Страница 1: ...OPERATION MANUAL CP1H CPU Unit SYSMAC CP Series CP1H X40D CP1H XA40D CP1H Y20DT D Cat No W450 E1 02...
Страница 2: ...CP1H X40D CP1H XA40D CP1H Y20DT D CP1H CPU Unit Operation Manual Revised May 2006...
Страница 3: ...iv...
Страница 11: ...xii TABLE OF CONTENTS...
Страница 15: ...xvi...
Страница 19: ...xx...
Страница 31: ...xxxii Conformance to EC Directives 6...
Страница 71: ...40 Function Blocks Section 1 5...
Страница 133: ...102 Computing the Cycle Time Section 2 7...
Страница 169: ...138 CPM1A Expansion I O Unit Wiring Section 3 6...
Страница 411: ...380 Clock Section 6 8...
Страница 519: ...488 Replacing User serviceable Parts Section 10 2...
Страница 527: ...496 Standard Models Appendix A...
Страница 535: ...504 Dimensions Diagrams Appendix B...
Страница 628: ...597 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Страница 629: ...598 Connections to Serial Communications Option Boards Appendix F...
Страница 659: ...628 PLC Setup Appendix G...
Страница 665: ...634 Index work words 159 write protection 370...
Страница 667: ...636 Revision History...