Motorola MPC8260 PowerQUICC II, Руководство пользователя

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MOTOROLA Chapter 14. Serial Interface with Time-Slot Assigner 14-17
Part IV. Communications Processor Module
14.5 Serial Interface Registers
The serial interface registers are described in the following sections. The MCC
conÞguration registers, which deÞne the TDM mapping of the MCC channels, are
described in Section 27.8, ÒMCC ConÞguration Registers (MCCFx).Ó Note that the
programming of SI registers and SI
x RAM must be coherent with the MCCF programming.
14.5.1 SI Global Mode Registers (SI x GMR)
The SI global mode registers (SI x GMR), shown in Figure 14-10, deÞnes the activation state
of the TDM channels for each SI.
Table 14-4 describes SI x GMR.
14.5.2 SI Mode Registers (SI x MR)
There are eight SI mode registers (SI x MR), shown in Figure 14-11, one for each TDM
channel (SI x AMR, SI x BMR, SI x CMR, and SI x DMR). They are used to deÞne SI operation
modes and allow the user (with SI x RAM) to support any or all of the ISDN channels
independently when in IDL or GCI mode. Any extra serial channel can then be used for
other purposes.
Bits 0 1 2 3 4 5 6 7
Field STZD STZC STZB STZA END ENC ENB ENA
Reset 0000_0000
R/W R/W
Addr 0x11B28 (SI1GMR), 0x11B48 (SI2GMR)
Figure 14-10. SI Global Mode Registers (SI x GMR)
Table 14-4. SI x GMR Field Descriptions
Bit Name Description
0Ð3 STZx Program L1TXDx to zero for TDM a, b, c or d
0 Normal operation
1 L1TXDx = 0 until serial clocks are available, which is useful for GCI activation. See Section 14.7.1,
ÒSI GCI Activation/Deactivation Procedure.Ó
4Ð7 ENx Enable TDMx. Note that enabling a TDM is the last step in initialization.
0 TDM channel x is disabled. The SI
x RAMs and routing for TDMx are in a state of reset, but all other
SI functions still operate.
1 All TDMx functions are enabled.