Motorola MPC8260 PowerQUICC II, Руководство пользователя

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MOTOROLA Chapter 33. Serial Peripheral Interface (SPI) 33-9
Part IV. Communications Processor Module
the data string selected is:
msb r_stuv__ghij_klmn lsb
with REV=0, the string transmitted, a byte at a time with lsb first is:
first vuts_r__nmlk_jihg last
with REV=1, the string is half-word reversed:
msb nmlk_jihg__vuts_r lsb
and transmitted a byte at a time with lsb first:
first ghij_klmn__r_stuv last
33.4.2 SPI Event/Mask Registers (SPIE/SPIM)
The SPI event register (SPIE) generates interrupts and reports events recognized by the SPI.
When an event is recognized, the SPI sets the corresponding SPIE bit. Clear SPIE bits by
writing a 1Ñwriting 0 has no effect. Setting a bit in the SPI mask register (SPIM) enables
and clearing a bit masks the corresponding interrupt. Unmasked SPIE bits must be cleared
before the CP clears internal interrupt requests. Figure 33-7 shows both registers.
Table 33-3 describes the SPIE/SPIM Þelds.
33.4.3 SPI Command Register (SPCOM)
The SPI command register (SPCOM), shown in Figure 33-8, is used to start SPI operation.
Bit 0 1 2 3 4 5 6 7
Field Ñ MME TXE Ñ BSY TXB RXB
Reset 0000_0000
R/W R/W
Addr 0x11AA6 (SPIE); 0x11AAA (SPIM)
Figure 33-7. SPIE/SPIMÑSPI Event/Mask Registers
Table 33-3. SPIE/SPIM Field Descriptions
Bits Name Description
0Ð1 Ñ Reserved, should be cleared.
2 MME Multimaster error. Set when SPISEL is asserted externally while the SPI is in master mode.
3 TXE Tx error. Set when an error occurs during transmission.
4 Ñ Reserved, should be cleared.
5 BSY Busy. Set after the Þrst character is received but discarded because no Rx buffer is available.
6 TXB Tx buffer. Set when the Tx data of the last character in the buffer is written to the Tx FIFO. Wait two
character times to be sure data is completely sent over the transmit signal.
7 RXB Rx buffer. Set after the last character is written to the Rx buffer and the BD is closed.