A-2
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Appendixes
A.2 PowerPC RegistersÑSupervisor Registers
All supervisor-level registers implemen
ted on the MPC8260 ar
e SPRs, except for the machine
state register (MSR), described in Table A-3
.
Table A-4 lists supervisor-level SPRs defined by the PowerPC architecture.
Table A-3. Supervisor-Level PowerPC Registers (Non-SPR)
Description
Name
Comments
Serialize Access
Machine state register
MSR
See the
Programming Environments Manual
and
MPC603e RISC Microprocessor UserÕs
Manual
Write fetch sync
Table A-4. Supervisor-Level PowerPC SPRs
SPR Number
Name
Comments
Serialize Access
Decimal
SPR[5Ð9]
SPR[0Ð4]
18
00000
10010
DSISR
See the
Programming Environments
Manual
Write: Full sync
Read: Sync relative to
load/store operations
19
00000
10011
DAR
See the
Programming Environments
Manual
Write: Full sync
Read: Sync relative to load/
store operations
22
00000
10110
DEC
See the
Programming Environments
Manual
Write
26
00000
11010
SRR0
See the
Programming Environments
Manual
Write
27
00000
11011
SRR1
See the
Programming Environments
Manual
Write
272
01000
10000
SPRG0
See the
Programming Environments
Manual
Write
273
01000
10001
SPRG1
274
01000
10010
SPRG2
275
01000
10011
SPRG3
284
01000
11100
TBL write
1
1
Any read (
mftb
) to this address causes an implementation-dependent software emulation exception.
See the
Programming Environments
Manual
Write (as a store)
285
01000
11101
TBU write
1
287
01000
11111
PVR
See Section 2.3.1.2.4, ÒProcessor
Version Register (PVR).Ó
No (read-only register)
Содержание MPC8260 PowerQUICC II
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