MOTOROLA
Chapter 10. Memory Controller
10-55
Part III. The Hardware Interface
Figure 10-45. GPCM Memory Device Basic Timing (ACS
¹
00, CSNT = 1, TRLX = 0)
10.5.1.3 Relaxed Timing
OR
x
[TRLX] is provided for memory systems that require more relaxed timing between
signals. When TRLX = 1 and ACS
¹
00, an additional cycle between the address and
strobes is inserted by the MPC8260 memory controller. See Figure
10-46 and
Figure 10-47.
Figure 10-46. GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, TRLX = 1)
Clock
Address
PSDVAL
CS
WE
Data
CSNT = 1
ACS = 11
ACS = 10
Clock
Address
PSDVAL
CS
R/W
WE
OE
Data
ACS = 10
ACS = 11
Содержание MPC8260 PowerQUICC II
Страница 1: ...MPC8260UM D 4 1999 Rev 0 MPC8260 PowerQUICC II UserÕs Manual ª ª ...
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Страница 88: ...1 18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
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Страница 138: ...Part II iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II Configuration and Reset ...
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Страница 202: ...Part III vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
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Страница 430: ...Part IV viii MOTOROLA Part IV Communications Processor Module ...
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Страница 980: ...A 4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Appendixes ...
Страница 1002: ...Index 22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA INDEX ...
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