MOTOROLA
Chapter 2. PowerPC Processor Core
2-19
Part I. Overview
PowerPC microprocessors control the following memory access modes on a page or block
basis:
¥
Write-back/write-through mode
¥
Caching-inhibited mode
¥
Memory coherency
The PowerPC cache management instructions provide a means by which the application
programmer can affect the cache contents.
2.4.2 MPC8260 Implementation-SpeciÞc Cache Implementation
As shown in Figure 2-1, the caches provide a 64-bit interface to the instruction fetch unit
and load/store unit. The surrounding logic selects, organizes, and forwards the requested
information to the requesting unit. Write operations to the cache can be performed on a byte
basis, and a complete read-modify-write operation to the cache can occur in each cycle.
Each cache block contains eight contiguous words from memory that are loaded from an
8-word boundary (that is, bits A27ÐA31 of the effective addresses are zero); thus, a cache
block never crosses a page boundary. Misaligned accesses across a page boundary can incur
a performance penalty.
The cache blocks are loaded in to the processor core in four beats of 64 bits each. The burst
load is performed as critical double word Þrst.
To ensure coherency among caches in a multiprocessor (or multiple caching-device)
implementation, the processor core implements the MEI protocol. These three states,
modiÞed, exclusive, and invalid, indicate the state of the cache block as follows:
¥
ModiÞedÑThe cache block is modiÞed with respect to system memory; that is, data
for this address is valid only in the cache and not in system memory.
¥
ExclusiveÑThis cache block holds valid data that is identical to the data at this
address in system memory. No other cache has this data.
¥
InvalidÑThis cache block does not hold valid data.
2.4.2.1 Data Cache
As shown in Figure 2-6, the data cache is conÞgured as 128 sets of four blocks each. Each
block consists of 32 bytes, two state bits, and an address tag. The two state bits implement
the three-state MEI (modiÞed/exclusive/invalid) protocol. Each block contains eight 32-bit
words. Note that the PowerPC architecture deÞnes the term ÔblockÕ as the cacheable unit.
For the MPC8260Õs processor core, the block size is equivalent to a cache line.
Содержание MPC8260 PowerQUICC II
Страница 1: ...MPC8260UM D 4 1999 Rev 0 MPC8260 PowerQUICC II UserÕs Manual ª ª ...
Страница 32: ...xxxii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS Paragraph Number Title Page Number ...
Страница 66: ...lxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA ...
Страница 88: ...1 18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Страница 120: ...2 32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Страница 138: ...Part II iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II Configuration and Reset ...
Страница 184: ...4 46 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II ConÞguration and Reset ...
Страница 202: ...Part III vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Страница 266: ...8 34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Страница 382: ...10 106 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Страница 392: ...11 10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Страница 430: ...Part IV viii MOTOROLA Part IV Communications Processor Module ...
Страница 490: ...14 36 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 524: ...17 10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 556: ...18 32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 584: ...19 28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 632: ...21 24 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 652: ...22 20 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 668: ...23 16 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 758: ...27 28 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 780: ...28 22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 874: ...29 94 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 920: ...31 18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part IV Communications Processor Module ...
Страница 980: ...A 4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Appendixes ...
Страница 1002: ...Index 22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA INDEX ...
Страница 1006: ......