Motorola MPC8260 PowerQUICC II, Руководство пользователя

Страница: 526 / 1006

18-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part IV. Communications Processor Module
On a path 1 access, the SDMA channel must acquire the external system bus. On a path 2
access, the local bus is acquired and the access is not seen on the external system bus. Thus,
the local bus transfer occurs at the same time as other operations on the external 60x system
bus.
The SDMA channel can be assigned abig-endian (Motorola) or little-endian format for
accessing buffer data. These features are programmed in the receive and transmit registers
associated with the FCCs, MCCs, SCCs, SMCs, SPI, and I
2
C.
If a 60x or local bus error occurs on a CP-related access by the SDMA, the CP generates a
unique interrupt in the SDMA status register (SDSR). The interrupt service routine then
reads the appropriate DMA transfer error address register (PDTEA for the 60x bus or
LDTEA for the local bus) to determine the address the bus error occurred on. The channel
that caused the bus error is determined by reading the channel number from PDTEM or
LDTEM. If an SDMA bus error occurs on a CP-related transaction, all CPM activity stops
and the entire CPM must be reset in the CP command register (CPCR). See Section 18.2,
ÒSDMA Registers.Ó
18.1 SDMA Bus Arbitration and Bus Transfers
On the MPC8260, the core and SDMA can become external bus masters. (The relative
priority of these masters is programmed by the user; see Section 4.3.2, ÒSystem
ConÞguration and Protection RegistersÓ for programming bus arbitration.) Therefore, any
SDMA channel can arbitrate for the bus against the other internal devices and any external
devices present. Once an SDMA channel becomes system bus master, it remains bus master
for one transaction (which can be a byte, half-word, word, burst, or extended special burst)
before releasing the bus. This feature, in combination with the zero-clock arbitration
overhead provided by the 60x bus, increases bus efÞciency and lowers bus latency.
To minimize the latency associated with slower, character-oriented protocols, an SDMA
writes each character to memory as it arrives without waiting for the next character, and
always reads using 16-bit half-word transfers.
The SDMA can access the 60x bus either at the regular 60x transactions (single-beat
accesses, four-beat bursts) or special two- and three-beat burst accesses. For a further
description of this feature see Section 8.4.3.8, ÒExtended Transfer Mode.Ó
A transfer may take multiple bus transactions if the memory provides a less than 64-bit 60x
port size or less than 32-bit local bus port size. An SDMA uses back-to-back bus
transactions for the entire transferÑ4-word bursts, 64-bit reads, and 8-, 16-, 32-, or 64-bit
writesÑbefore relinquishing the bus. For example, a 64-bit word 60x-bus read from a 32-
bit memory takes two consecutive SDMA bus transactions.
An SDMA can steal transactions with no arbitration overhead when the MPC8260 is bus
master. Figure 18-2 shows an SDMA stealing a transaction from an internal bus master.