Motorola MPC8260 PowerQUICC II, Руководство пользователя

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MOTOROLA Chapter 10. Memory Controller 10-5
Part III. The Hardware Interface
Ñ Each UPM can be deÞned to support DRAM devices with depths of 64, 128, 256,
and 512 Kbytes, and 1, 2, 4, 8, 16, 32, 64, 128, and 256 Mbytes
Ð Chip-select line
Ð Byte-select lines
Ð Six external general-purpose lines
Ñ Supports 8-, 16-, 32-, and 64-bit memory port sizes, 8-, 16-, and 32-bit port sizes
on the local bus
Ñ Page mode support for successive transfers within a burst
Ñ Internal address multiplexing for all on-chip bus masters supporting 64-, 128-,
256-, and 512-Kbyte, and 1-, 2-, 4-, 8-, 16-, 32-, 64-, 128-, 256-Mbyte page
banks
10.2 Basic Architecture
The memory controller consists of three basic machines:
¥ Synchronous DRAM machine
¥ General-purpose chip-select machine (GPCM)
¥ Three UPMs
Each bank can be assigned to any one of these machines via BR x [MS] as shown in
Figure 10-2. The MS and M x MR[BS] bits (for UPMs) assign banks to the 60x bus or local
bus, as shown in Figure 10-2. Addresses are decoded by comparing (A[0Ð16] bit-wise and
OR
x [AM]) with BR x [BA]. If an address match occurs in multiple banks, the lowest
numbered bank has priority. However, if a 60x bus access hits a bank allocated to the local
bus, the access is transferred to the local bus. Local bus access hits to 60x assigned banks
are ignored.
When a memory address matches BR x [BA], the corresponding machine takes ownership
of the external signals that control access and maintains control until the cycle ends.