Motorola MPC8260 PowerQUICC II, Руководство пользователя

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MOTOROLA Chapter 8. The 60x Bus 8-21
Part III. The Hardware Interface
bus, but some slaves or masters do not support these features. Clear BCR[ETM] to disable
this type of transaction. This places the MPC8260 in strict 60x bus mode. The following
tables are extensions to Table 8-9, Table 8-8, and Table 8-10.
Table 8-11 lists the patterns of the extended data transfer for write cycles when MPC8260
initiates an access. Note that 16- and 24-byte transfers are always eight-byte aligned and
use a 64-bit or less port size.
Table 8-12 lists the bytes required on the data bus for extended read cycles. Note that 16-
and 24-byte transfers are always 8-byte aligned and use a maximum 64-bit port size.
Table 8-13 includes added states to the transfer size calculation state machine. Only
extended transfers use these states.
Table 8-11. Data Bus Contents for Extended Write Cycles
Transfer
Size
TSIZ[0Ð3])
Address
State A[29Ð
31]
External Data Bus Pattern
D[0Ð7] D[8Ð15] D[16Ð23] D[24Ð31] D[32Ð39] D[40Ð47] D[48Ð55] D[56Ð63]
5 Bytes
(0101)
000 OP0 OP1 OP2 OP3 OP4 Ñ Ñ Ñ
011 OP3 OP3 Ñ OP3 OP4 OP5 OP6 OP7
6 Bytes
(0110)
000 OP0 OP1 OP2 OP3 OP4 OP5 Ñ Ñ
010 OP2 OP3 OP2 OP3 OP4 OP5 OP6 OP7
7 Bytes
(0111)
000 OP0 OP1 OP2 OP3 OP4 OP5 OP6 Ñ
001 OP1 OP1 OP2 OP3 OP4 OP5 OP6 OP7
Table 8-12. Data Bus Requirements for Extended Read Cycles
Transfer
Size
TSIZ[0Ð3]
Address
State
A[29-31]
Port Size/Data Bus Assignments
64-Bit 32-Bit 16-Bit 8-Bit
0Ð7 8Ð15 16Ð23 24Ð31 32Ð39 40Ð47 48Ð55 56Ð63 0Ð7 8Ð15 16Ð23 24Ð31 0Ð7 8Ð15 0Ð7
5 Byte
(0101) 000 OP0 OP1 OP2 OP3 OP4 Ñ Ñ Ñ OP0 OP1 OP2 OP3 OP0 OP1 OP0
011 Ñ Ñ Ñ OP3 OP4 OP5 OP6 OP7 Ñ Ñ Ñ OP3 Ñ OP3 OP3
6 Byte
(0110) 000 OP0 OP1 OP2 OP3 OP4 OP5 Ñ Ñ OP0 OP1 OP2 OP3 OP0 OP1 OP0
010 Ñ Ñ OP2 OP3 OP4 OP5 OP6 OP7 Ñ Ñ OP2 OP3 OP2 OP3 OP2
7 Byte
(0111) 000 OP0 OP1 OP2 OP3 OP4 OP5 OP6 Ñ OP0 OP1 OP2 OP3 OP0 OP1 OP0
001 Ñ OP1 OP2 OP3 OP4 OP5 OP6 OP7 Ñ OP1 OP2 OP3 Ñ OP1 OP1