MOTOROLA
Chapter 8. The 60x Bus
8-15
Part III. The Hardware Interface
The MPC8260 supports misaligned memory operations, although they may degrade
performance substantially. A misaligned memory address is one that is not aligned to the
size of the data being transferred (such as, a word read from an odd byte address). The
MPC8260Õs processor bus interface supports misaligned transfers within a word (32-bit
aligned) boundary, as shown in Table 8-7. Note that the 4-byte transfer in Table 8-7 is only
one example of misalignment. As long as the attempted transfer does not cross a word
boundary, the MPC8260 can transfer the data to the misaligned address within a single bus
transfer (for example, a half-word read from an odd byte-aligned address). It takes two bus
transfers to access data that crosses a word boundary.
Due to the performance degradation, misaligned memory operations should be avoided. In
addition to the double-word straddle boundary condition, the processorÕs address
translation logic can generate substantial exception overhead when the load/store multiple
and load/store string instructions access misaligned data. It is strongly recommended that
Table 8-6. Aligned Data Transfers
Program Transfer
Size
TSIZ[0Ð3]
A[29Ð31]
Data Bus Byte Lanes
D0... ...D31
D32... ...D63
B0
B1
B2
B3
B4
B5
B6
B7
Byte
0 0 0 1
0 0 0
OP0
1
1
OP
n
: These lanes are read or written during that bus transaction. OP0 is the most-signiÞcant byte of a word
operand and OP7 is the least-signiÞcant byte.
Ñ
2
2
Ñ: These lanes are ignored during reads and driven with undeÞned data during writes.
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
0 0 0 1
0 0 1
Ñ
OP1
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
0 0 0 1
0 1 0
Ñ
Ñ
OP2
Ñ
Ñ
Ñ
Ñ
Ñ
0 0 0 1
0 1 1
Ñ
Ñ
Ñ
OP3
Ñ
Ñ
Ñ
Ñ
0 0 0 1
1 0 0
Ñ
Ñ
Ñ
Ñ
OP4
Ñ
Ñ
Ñ
0 0 0 1
1 0 1
Ñ
Ñ
Ñ
Ñ
Ñ
OP5
Ñ
Ñ
0 0 0 1
1 1 0
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP6
Ñ
0 0 0 1
1 1 1
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP7
Half-Word
0 0 1 0
0 0 0
OP0
OP1
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
0 0 1 0
0 1 0
Ñ
Ñ
OP2
OP3
Ñ
Ñ
Ñ
Ñ
0 0 1 0
1 0 0
Ñ
Ñ
Ñ
Ñ
OP4
OP5
Ñ
Ñ
0 0 1 0
1 1 0
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
OP6
OP7
Word
0 1 0 0
0 0 0
OP0
OP1
OP2
OP3
Ñ
Ñ
Ñ
Ñ
0 1 0 0
1 0 0
Ñ
Ñ
Ñ
Ñ
OP4
OP5
OP6
OP7
Double-Word
0 0 0 0
0 0 0
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
Содержание MPC8260 PowerQUICC II
Страница 1: ...MPC8260UM D 4 1999 Rev 0 MPC8260 PowerQUICC II UserÕs Manual ª ª ...
Страница 32: ...xxxii MPC8260 PowerQUICC II UserÕs Manual MOTOROLA CONTENTS Paragraph Number Title Page Number ...
Страница 66: ...lxvi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA ...
Страница 88: ...1 18 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Страница 120: ...2 32 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part I Overview ...
Страница 138: ...Part II iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II Configuration and Reset ...
Страница 184: ...4 46 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II ConÞguration and Reset ...
Страница 202: ...Part III vi MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Страница 266: ...8 34 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Страница 382: ...10 106 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Страница 392: ...11 10 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part III The Hardware Interface ...
Страница 430: ...Part IV viii MOTOROLA Part IV Communications Processor Module ...
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Страница 980: ...A 4 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Appendixes ...
Страница 1002: ...Index 22 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA INDEX ...
Страница 1006: ......