Motorola MPC8260 PowerQUICC II, Руководство пользователя

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7-12 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA
Part III. The Hardware Interface
7.2.6 Data Bus Arbitration Signals
The data bus arbitration signals have no meaning in internal-only mode.
Like the address bus arbitration signals, data bus arbitration signals maintain an orderly
process for determining data bus mastership. Note that there is no data bus arbitration signal
equivalent to the address bus arbitration signal BR (bus request), because, except for
address-only transactions, TS implies data bus requests. For a detailed description on how
these signals interact, see Section 8.5.1, ÒData Bus Arbitration.Ó
7.2.6.1 Data Bus Grant (DBG)
The data bus grant signal (DBG) is an output/input on the MPC8260
7.2.6.1.1 Data Bus Grant (DBG)ÑInput
DBG an input when MPC8260 is conÞgured to an external arbiter. The following are the
state meaning and timing comments for DBG.
State Meaning AssertedÑIndicates that the MPC8260 may, with the proper
qualiÞcation, assume mastership of the data bus. The MPC8260
derives a qualiÞed data bus grant when DBG is asserted and DBB
and ARTRY are negated; that is, the data bus is not busy (DBB is
negated), and there is no outstanding attempt to perform an ARTRY
of the associated address tenure.
NegatedÑIndicates that the MPC8260 must hold off its data tenures.
Timing Comments AssertionÑMay occur any time to indicate the MPC8260 is free to
take data bus mastership. It is not sampled until TS is asserted.
NegationÑMay occur at any time to indicate the MPC8260 cannot
assume data bus mastership.
7.2.6.1.2 Data Bus Grant (DBG)ÑOutput
DBG signal is output when the MPC8260 conÞgured to Internal Arbiter. Following are the
state meaning and timing comments for the DBG signal.
State Meaning AssertedÑIndicates that the external device may, with the proper
qualiÞcation, assume mastership of the data bus. A qualiÞed data bus
grant is deÞned as the assertion of DBG, negation of DBB, and
negation of ARTRY. The requirement for the ARTRY signal is only
for the address bus tenure associated with the data bus tenure about
to be granted (that is, not for another address tenure available
because of address pipelining).
NegatedÑIndicates that an external device is not granted mastership
of the data bus.
Timing Comments AssertionÑOccurs on the Þrst clock in which the data bus is not
busy and the processor has the highest priority outstanding data
transaction.
NegationÑOccurs one clock after assertion.