Motorola MPC8260 PowerQUICC II, Руководство пользователя

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MOTOROLA Chapter 10. Memory Controller 10-33
Part III. The Hardware Interface
10.3.13 60x Bus Error Status and Control Registers (TESCR x )
These registers indicate the source of an error that caused TEA or MCP to be asserted on
the 60x bus. See Section 4.3.2.10, Ò60x Bus Transfer Error Status and Control Register 1
(TESCR1),Ó and Section 4.3.2.11, Ò60x Bus Transfer Error Status and Control Register 2
(TESCR2).Ó
10.3.14 Local Bus Error Status and Control Registers (L_TESCR x )
These registers indicate the source of an error that causes TEA or MCP to be asserted on
the local bus. See Section 4.3.2.12, ÒLocal Bus Transfer Error Status and Control Register 1
(L_TESCR1),Ó and Section 4.3.2.13, ÒLocal Bus Transfer Error Status and Control
Register 2 (L_TESCR2).Ó
10.4 SDRAM Machine
The MPC8260 provides one SDRAM interface (machine) for the 60x bus and one for the
local bus. The machines provide the necessary control functions and signals for
JEDEC-compliant SDRAM devices.
Each bank can control a SDRAM device on the 60x or the local bus. Table 10-17 describes
the SDRAM interface signals controlled by the memory controller.
Additional controls are available in 60x-compatible mode (60x bus only):
¥ ALEÑExternal address latch enable
¥ PSDAMUXÑExternal address multiplexing control (asserted = row,
negated = column)
¥ BNKSEL[0Ð2]ÑBank select address to allow internal bank interleaving
Throughout this section, whenever a signal is named, the reference is to the 60x or local bus
signal, according to the accessed bankÕs machine-select.
Figure 10-19 shows an eight-bank, 128-Mbyte system. Each bank consists of eight 2 x
1-Mbit x 8 SDRAMs. Note that the SDRAM memory clock must operate at the same
frequency as, and be phase-aligned with, the system clock.
Table 10-17. SDRAM Interface Signals
60x Bus Local Bus Comments
CS[0Ð11] Device select
PSDRAS LSDRAS RAS
SDCAS LSDCAS CAS
SDWE LSDWE WEN
SDA10 LSDA10 ÒA10Ó control
DQM[0Ð7] LDQM[0Ð3] Byte select