19-14
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
Part IV. Communications Processor Module
0x06
MRBLR
Hword Maximum receive buffer length. DeÞnes the maximum number of bytes the MPC8260
writes to a receive buffer before it goes to the next buffer. The MPC8260 can write fewer
bytes than MRBLR if a condition such as an error or end-of-frame occurs. It never writes
more bytes than the MRBLR value. Therefore, user-supplied buffers should be no
smaller than MRBLR. MRBLR should be greater than zero for all modes. It should be a
multiple of 4 for Ethernet and HDLC modes, and in totally transparent mode unless the
Rx FIFO is 8-bits wide (GSMR_H[RFW] = 1).
Note that although MRBLR is not intended to be changed while the SCC is operating, it
can be changed dynamically in a single-cycle, 16-bit move (not two 8-bit cycles).
Changing MRBLR has no immediate effect. To guarantee the exact Rx BD on which the
change occurs, change MRBLR only while the receiver is disabled.
Transmit buffer length is programmed in TxBD[Data Length] and is not affected by
MRBLR.
0x08
RSTATE
Word
Rx internal state
3
0x0C
Word
Rx internal buffer pointer
2
. The Rx and Tx internal buffer pointers are updated by the
SDMA channels to show the next address in the buffer to be accessed.
0x10
RBPTR
Hword Current RxBD pointer. Points to the current BD being processed or to the next BD the
receiver uses when it is idling. After reset or when the end of the BD table is reached,
the CPM initializes RBPTR to the value in the RBASE. Although most applications do
not need to write RBPTR, it can be modiÞed when the receiver is disabled or when no
Rx buffer is in use.
0x12
Hword Rx internal byte count
2
. The Rx internal byte count is a down-count value initialized with
MRBLR and decremented with each byte written by the supporting SDMA channel.
0x14
Word
Rx temp
3
0x18
TSTATE
Word
Tx internal state
3
0x1C
Word
Tx internal buffer pointer
2
. The Rx and Tx internal buffer pointers are updated by the
SDMA channels to show the next address in the buffer to be accessed.
0x20
TBPTR
Hword Current TxBD pointer. Points to the current BD being processed or to the next BD the
transmitter uses when it is idling. After reset or when the end of the BD table is reached,
the CPM initializes TBPTR to the value in the TBASE. Although most applications do not
need to write TBPTR, it can be modiÞed when the transmitter is disabled or when no Tx
buffer is in use (after a
STOP
TRANSMIT
or
GRACEFUL
STOP
TRANSMIT
command is issued
and the frame completes its transmission).
0x22
Hword Tx internal byte count
2
. A down-count value initialized with TxBD[Data Length] and
decremented with each byte read by the supporting SDMA channel.
0x24
Word
Tx temp
3
0x28
RCRC
Word
Temp receive CRC
2
0x2C
TCRC
Word
Temp transmit CRC
2
0x30
Protocol-speciÞc area. (The size of this area depends on the protocol chosen.)
1
From SCC base. See Section 19.3.1, ÒSCC Base Addresses.Ó
2
These parameters need not be accessed for normal operation but may be helpful for debugging.
3
For CP use only
Table 19-4. SCC Parameter RAM Map for All Protocols (Continued)
Содержание MPC8260 PowerQUICC II
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Страница 138: ...Part II iv MPC8260 PowerQUICC II UserÕs Manual MOTOROLA Part II Configuration and Reset ...
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