High-Level Data Link Control (HDLC)
15-8
Am186™CC/CH/CU Microcontrollers User’s Manual
3. Set the necessary transmit enables (HxTXON0 register) and receive enables
(HxRCON0 register) for each HDLC channel.
4. Do an HDLC reset. A reset flushes the FIFOs and clears all R/0 status bits, but does
not clear the R/W0 interrupt status registers.
5. Clear all pending interrupts by writing 0s to the INTSTS register.
15.5.2
Interface
The HDLC channels operate in one of two modes: SmartDMA data transfer or programmed
I/O. SmartDMA data transfer provides automated data movement to the transmit FIFO or
from the receive FIFO. Programmed I/O is intended for low data rates where processor
intervention is possible on a byte-by-byte basis.
15.5.2.1
SmartDMA Interface
Using the SmartDMA interface bypasses the HDLC status registers associated with data
handling (HxSTATE, HxISTAT0, HxISTAT1, HxRFS1, HxRFS2, HxRFS3, HxASBMSB,
HxASBLSB) because the SmartDMA interface automatically places all data and status to
and from the data buffers and buffer descriptors residing in memory. Some applications still
require additional status such as the link status. For more information about the SmartDMA
interface, see Chapter 8, “DMA Controller.”
15.5.2.2
Programmed I/O Interface
15.5.2.2.1
Transmit Programmed I/O Interface
To transmit a frame using programmed I/O, first program the control registers with the
appropriate mode(s), then enable the transmitter. Then, either poll a status bit indicating
transmit space is available or use the transmit space available interrupt to determine when
space is available in the transmit FIFO. Just after writing the last byte of a frame to the
transmit FIFO, set the “last byte” bit in the control register. When the last byte in the frame
is written to the transmit FIFO, the HDLC controller knows to append the CRC (if enabled)
and closing flag. When the last byte of the frame has been transmitted, the transmitter
generates a maskable interrupt and sets a status bit.
The interrupt register indicates if there was an underflow of the transmit FIFO, if CTS was
lost during transmission, or if the transmit frame was aborted during transmission. When
one of these conditions occurs, the HDLC controller flushes the transmit FIFO and stops
the transmitter until the appropriate status bit is cleared.
15.5.2.2.2
Receive Programmed I/O Interface
To receive a frame using programmed I/O, first program the control registers with the
appropriate mode(s) and then enable the receiver. Then, either poll a status bit (one receive
data byte available) or take an interrupt (receive threshold reached or data byte available)
to determine that data is available in the receive FIFO. This data can then be read from the
receive FIFO interface register. A different status bit (received end of frame) is active to
indicate that frame status is now available in the receive FIFO. A maskable interrupt is also
generated. The status consists of three bytes: the first two bytes are the frame byte count
and the last byte is the general frame status. When performing a word (16-bit) read of the
FIFO, the lower byte contains the data and the upper byte indicates whether the lower byte
is data or status byte one, two, or three. The upper byte also indicates whether the
programmed FIFO threshold has been reached and if any interrupts are pending.
Содержание Am186 CC
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Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...