Asynchronous Serial Ports (UARTs)
Am186™CC/CH/CU Microcontrollers User’s Manual
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frame. At the end of the receipt of a sequence of frames, software can examine the value
of the (H)SPSTAT register to determine if any significant status bits have been set. If the
accumulated status does not reflect action required by software, the status bytes can be
ignored, otherwise software can traverse the buffer searching for the status of interest and
its associated data byte.
The microcontroller’s general-purpose DMA channels support compression and
decompression of data streams in part to support the extended read and write features of
the serial ports. Status can be removed from a data stream through data compression using
the DMA. For more information, see Chapter 8, “DMA Controller.”
13.5.3
FIFOs (High-Speed UART Only)
The High-Speed UART provides a 32-byte FIFO for receive data and a 16-byte FIFO for
transmit data. The use of the FIFOs can be enabled or disabled by software. The FIFOs
can be operated in Polled or Interrupt mode, or they can be serviced using the general-
purpose DMA channels. The High-Speed UART status register provides the RTHRSH and
TTHRSH bits, which reflect the state of the receive and transmit FIFOs, respectively. When
the RTHRSH bit is set, the receive FIFO has reached its threshold value (i.e., the receive
FIFO is at least half full). When the THRSH bit is set, the transmit FIFO has reached its
threshold value (i.e., the transmit FIFO is at least half empty). The HSPIMSK register
contains bits that enable or disable interrupt generation based on the RTHRSH and
TTHRSH bits. In this case, interrupt generation on the RDR (Receive Data Ready) and
THRE (Transmit Holding Register Empty) bits should be disabled.
FIFOs are initialized to the empty condition on reset. For subsequent transfers, the transmit
FIFO and the receive FIFO should be flushed by software by setting the TFLUSH and
RFLUSH bits in the HSPCON1 register.
All transmit data is written to a single address, which is addressable as the transmit data
register (HSPTXD) in both FIFO and non-FIFO modes. When the FIFO is not full, the High-
Speed UART status register has the THRE bit set, indicating that data can be written to the
FIFO without overwriting previously written data.
Receive data is read from a single address, which is addressable as the High-Speed UART
Receive Data (HSPRXD) register in both FIFO and non-FIFO modes. When the FIFO is
not empty, valid data can be read from HSPRXD; this is indicated by the Receive Data
Ready (RDR) bit in the HSPSTAT status register. When the last bit of data has been removed
from the FIFO, the RDR bit reads 0.
The status associated with each of the FIFO entries can be determined by reading the
Serial Port Status (HSPSTAT) register before the associated data is read from the FIFO.
When a byte is read from the FIFO, the next received character and its status move to the
top of the FIFO and can be read from the receive data and status registers. The status must
be read before the data is read. Alternatively, extended reads can be enabled. Extended
reads allow status to be read with data as it moves to the top of the FIFO. Reading the
status using extended reads differs from what is shown in the serial port status register in
that it reflects the current frame only. The serial port status register functions normally during
extended reads and continues to reflect accumulated status and to generate interrupts
based on that status as configured.
13.5.3.1
Transmit FIFO
The transmit FIFO provides for up to 16 bytes of transmit data plus the value of the
associated address bit, if applicable.
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Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...