High-Level Data Link Control (HDLC)
15-16
Am186™CC/CH/CU Microcontrollers User’s Manual
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Short-Frame Counter: The HxSFCNT and HxSFCNTP registers indicate the total
number of short frames received. The HxSFCNT register clears when read; HxSFCNTP
does not. This count also includes all very short frames. If the counter rolls over, it
generates a maskable interrupt. This count does not include frames with mismatched
addresses.
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CRC Checker: When the receiver detects the closing flag, it examines the 16-bit (or 32-
bit) CRC. If it detects an error, it reports a status bit to that effect. The receiver supports
the CRC-CCITT, CRC-16, and CRC-32 algorithms. The receiver always places the CRC
in the FIFO along with the rest of the frame data (that is, all data between flags is placed
in the FIFO). The CRC checker is always enabled, but software can ignore the CRC
error status (byte 3 of the status read from the HxRD register). Specify the CRC type in
the CRCTYPE field of the HxCON register.
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Serial-to-Parallel Shift Register: Output from the zero-bit-deletion unit feeds into a 16-
bit shift register, which converts the serial stream into bytes. The receiver then feeds the
parallel output of the shift register to the receive FIFO one byte at a time.
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Address Detection: The receiver uses address detection to determine whether to
receive the current frame. Each HDLC channel has four 16-bit matching address
registers (the HxA0–HxA3 registers) and four corresponding 16-bit matching address
mask registers (the HxA0MSK–HxA3MSK registers). The mask register determines
which of the first 16 data bits in the frame the receiver should compare to the
corresponding address register and which to ignore. If all unmasked bits of at least one
address match, the receiver accepts the frame; otherwise, it discards the frame and
starts looking for the next flag. The frame status byte contains information about which
address matched.
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Mismatch-Address Counter: The HxMACNT and HxMACNTP registers keep count of
the number of frames that did not have an address match. The HxMACNT register clears
when read; HxMACNTP does not. Count rollover generates a maskable interrupt. The
receiver checks all frames two bytes or larger for an address match. The receiver does
not check the discarded very short frames.
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Receive FIFO: The receive FIFO consists of a 32-byte FIFO buffer, end-of-frame logic,
and DMA-request logic. Read the receive FIFO at the HxRD register.
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Receive-FIFO Interface: The receiver uses either programmed I/O or the DMA
controller to unload the receive FIFO. In programmed I/O mode, the RDATA1 bit of the
HxISTAT0 register indicates when data is ready to be read from the receive FIFO. Data
ready also generates a maskable interrupt. The REOF bit of the HxISTAT0 register (and
a maskable interrupt) indicate when the frame status from the last frame received is
available to be read from the receive FIFO and data is no longer ready to be read. The
next frame data is not available until that status bit is cleared. The SmartDMA interface
automatically moves the frame status to the buffer descriptors at the end of the frame.
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Receive-FIFO Threshold: The receive FIFO supports thresholds of 1, 8, 16, or 32 bytes
under program control. Specify the receive FIFO threshold in the RTHRSH field of the
HxRCON0 register. The SmartDMA interface does not move data to memory until the
receive FIFO threshold is reached, indicated by the RTHRES bit of the HxISTAT0 register.
When the receive FIFO reaches the programmed threshold level, the data ready status
stays set until the receive FIFO is empty. At the end of a frame, the receive FIFO outputs
the remainder of the frame even if the receive FIFO threshold is not met.
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Receive-Data Available: For programmed I/O, the RDATA1 bit of the HxISTAT0 register
indicates when there is a data byte presently available in the receive FIFO. This indication
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...