Watchdog Timer
11-4
Am186™CC/CH/CU Microcontrollers User’s Manual
11.5.2
Overview
Because the watchdog timer is enabled after reset, it is important for start-up code to
program the watchdog timer before the initial time-out period expires. The time-out period
after a watchdog timer reset is 2
26
clock cycles.
All writes to the WDTCON register must be preceded by the write key sequence. The write
key is a special two-write sequence to the WDTCON register address. The value of the key
is not written to the WDTCON register but is used by internal logic to open the register for
a single write. If a read-modify-write sequence is desired, the read must take place before
the key is written because a read of WDTCON resets the keyed sequence.
The system’s start-up code can either enable or disable the watchdog timer. When enabled,
the watchdog timer cannot be disabled until a reset occurs. If disabled, it can be enabled
later by software. The reset start-up code should check the WDTCON register to see if the
RSTFLAG bit is set. If set, then the last reset was due to a watchdog timer time-out. What
actions are taken is system dependent; however, possible actions include signaling another
device that there is a problem, performing a more extensive test of hardware systems, or
requesting reset of remote devices.
Debug monitor software (such as AMD’s E86MON™ software) can disable the watchdog
timer, allowing the user to interact with the monitor without having to refresh the watchdog
timer. The application code can then enable or disable the watchdog timer in its own start-
up routine.
In systems that program the watchdog timer to generate an NMI, the NMI service routine
should check the WDTCON register to see if the NMIFLAG bit is set. If this bit is set, it
indicates that an NMI due to a watchdog timer time-out occurred. Software should clear
this bit so that subsequent external NMIs are not confused with watchdog timer NMIs. What
actions are taken are system dependent; however, possible actions include examining the
state of the DMA controller to determine whether DMA usage is preventing instruction
execution, polling external devices for status, or re-execution of all or part of the system
start-up code.
Code that supports the watchdog timer should be divided into two parts. The main loop of
the application, or some section of code that is periodically executed but not interrupt driven,
should set a flag indicating that execution has passed through this code loop. A second
piece of code that is interrupt driven, typically a timer interrupt, should check the value of
the flag. If the flag is set, the interrupt service routine (ISR) should write the watchdog timer
clear-count key, resetting the time-out counter to zero. If the flag is not set, the ISR has
several options: wait for a watchdog timer time-out to let the reset or NMI code handle the
problem; attempt to determine what the problem is; or continue normal execution with the
expectation that the flag may be set at some later iteration. Because transfer of control to
an ISR does not require non-ISR code to be executing correctly, it is important that the ISR
code not reset the time-out counter unless the flag is set.
11.5.3
Hardware-Related Considerations
■
Pins that are latched on reset (pinstraps) are not resampled during a watchdog-timer
reset.
■
If the external reset (RES) signal is asserted while the watchdog timer is performing a
watchdog-timer reset, the external reset takes precedence over the watchdog-timer
reset. This means that the RESOUT signal asserts as with any external reset and the
WDTCON register does not have the RSTFLAG bit set. In addition, the part exits reset
based on the external reset timing (i.e., 4.5 clocks after the deassertion of RES rather
than 2
16
clocks after the watchdog timer time-out occurred).
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...