Glossary
Am186™CC/CH/CU Microcontrollers User’s Manual
Glossary-3
DRAM
Dynamic random access memory. A type of computer
memory that employs a system of transistors and
capacitors to retain data. DRAM is slower and less
dependable than static RAM because the capacitors
cannot maintain an electrical charge and need to be
refreshed every millisecond, but it is cheaper, takes up
less space, and uses less power.
Compare to
SRAM.
DSL
Digital subscriber line. A modem technology that
increases the digital speed of ordinary telephone lines
by a substantial factor over common V.34 (33600 bps)
modems. DSL modems may provide symmetrical or
asymmetrical (ADSL) operation. Asymmetrical provides
faster downstream speeds and is suited for internet
usage and video on demand, where the heaviest trans-
mission requirement is from the provider to the
customer.
DSL uses packet switching technology that operates
independently from the voice telephone system. This
allows the telephone companies to provide digital ser-
vice and not lock up voice circuits for long calls.
Because of this, DSL is not as well suited to videocon-
ferencing as is ISDN. ISDN is circuit switched, which
keeps the line open and connected throughout the
session.
DTE
Data terminal equipment. A hardware component con-
nected to some type of communications device. A PC is
a piece of data terminal equipment; a modem is a com-
munications device.
duplex
The ability of a serial communications connection to
transmit data in both directions.
See also
half duplex
and
full duplex
. Compare to
simplex
.
E
EDO
Extended data out.
endpoint
See
USB endpoint.
endpoint address
The combination of a device address and an endpoint
number on a USB device.
endpoint number
A unique pipe endpoint on a USB device.
EOM
End of message.
even parity
Se
e parity.
external reset
The reset of the Am186CC/CH/CU microcontrollers ini-
tiated by asserting the RES signal. Also called a power-
on reset.
Compare to
internal reset
and
system reset.
F
FCS
Frame check sequence. The FCS contains the gener-
ated CRC code for the frame being transmitted. All data
transmitted between the opening and closing flags
(excluding inserted 0s) is included in the CRC calcula-
tion. The transmitter appends the calculated CRC to the
end of the frame just before the closing flag.
FIFO
First in first out. (1) Describes a method of processing
data in the order in which it is received. (2) A block of
memory or other storage used as a first-in-first-out
buffer.
FIFO high-water mark
See
FIFO threshold
.
FIFO threshold
A system-dependent, software threshold value that indi-
cates action should be taken so data is not lost from the
FIFO buffer.
fly-by-transfer
During a SmartDMA channel transfer, the read and
write operations execute in a single bus cycle, instead of
the two cycles required during a general-purpose DMA
transfer.
frame
The unit of information transferred across a data link.
Typically, there are control frames for link management
and information frames for the transfer of message
data.
frame synchronization (frame sync)
During an HDLC transfer, the process of signaling the
beginning of the frame with a start flag and the end of
the frame with a stop flag.
framing error
In asynchronous serial communication, a condition
resulting from the receiver losing bit count alignment
with the transmitter. In this situation, if the last bit of a
unit (a frame) is a zero, the receiver may read that bit as
the start bit of the next frame, thus the term framing
error.
full duplex
The ability of a serial communications connection to
transmit data in both directions at the same time.
See
also
duplex
and
simplex.
Compare to
half duplex.
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...