DMA Controller
8-42
Am186™CC/CH/CU Microcontrollers User’s Manual
8.5.7.8
SmartDMA Channel Interrupts
SmartDMA channels can generate interrupts based on three conditions. The interrupt
remains pending until software clears the associated status bit(s).
The following list shows the different interrupt types, and gives some useful information
about the characteristics of the interrupt.
■
TEPI and REPI (Transmit/Receive End of Packet) interrupts are asserted when the last
byte of a packet is transmitted or received. If many of the packets are short or appear
to be short (e.g., due to an excessively noisy communications line), then the frequency
of the interrupts may be higher than desired.
■
TTCI and RTCI (Transmit/Receive Terminal Count) interrupts are asserted when the last
byte of a buffer is transmitted or received. The TTCE/RTCE bit in word 2 of the descriptor
entry must also be set to use this interrupt.
Because generation of this interrupt is controllable on a buffer-by-buffer basis, it can be
set up so that an interrupt occurs every
n buffers, where n is completely under software
control. This can be a useful way to reduce frequency of interrupts while ensuring that
there are always descriptors available for the hardware. However, relying solely on this
interrupt for a receive descriptor chain could mean that up to the last
n–1 buffers in the
ring go unprocessed.
If RTCI is the primary interrupt for a receive descriptor ring, a timer interrupt can also
be used to detect leftover buffers after the other side has stopped sending. This can be
a one-shot timer that is reset on every RTC interrupt, so that the timer expires shortly
after the next RTC interrupt is expected. This timer interrupt generally should not be
required on transmit descriptor rings, because any system that wants to be interrupted
after there are no more buffers in the ring to send out can rely on the TBUI interrupt (see
the description below).
■
TBUI and RBUI (Transmit/Receive Buffer Unavailable) interrupts are asserted when an
attempt to load the next descriptor in the ring finds that the OWN bit is 0.
As discussed above, TBUI can be used to determine if all buffers have been sent. You
should not rely on RBUI interrupts to cause software to make more buffers available to
the hardware, or on TBUI interrupts to cause software to make additional buffers within
a single packet available to the hardware. The interrupt latency associated with either
of these tasks could cause FIFO overflows or underruns. RBUI can be used as a type
of watchdog interrupt—if RBUI interrupts are occurring, it means that, for some reason,
the system is not giving the receiver buffers fast enough.
8.5.7.9
SmartDMA Channel Use Without CPU Intervention
In each SmartDMA channel, the user has the option of not clearing the OWN bit after DMA
has finished accessing a buffer (with the TXS0 and RXS0 bits in the SDxCON register).
This option provides the effect of a circular buffer from which data is accessed without the
intervention of software.
In a typical scenario, an HDLC receive channel and a different HDLC transmit channel, or
an HDLC receive channel and a USB IN endpoint, share a circular buffer. This shared buffer
is implemented in software by making the transmit DMA channel read from the same
memory area to which the receive DMA channel is writing. A software PLL attempts to keep
the write pointer slightly ahead of the read pointer so that stale data is never read by the
transmitter, and so that the receiver never overwrites data not yet transmitted. In case of
an error, both the transmit and receive channel can be disabled and reprogrammed to start
at any particular buffer descriptor in the ring.
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...