Synchronous Serial Port (SSI)
14-6
Am186™CC/CH/CU Microcontrollers User’s Manual
signal. Setting DE0 asserts the SDEN signal. Asserting SDEN enables the external device
to which this signal is connected for communication on the SSI. Writing the transmit register
or reading the receive register initiates a data transfer on the SSI.
Software can configure the SDEN signal to be active High or Low with the DENP bit in the
SSCON register.
For a receive operation, reading the SSRXD register when the synchronous serial data
enable bits DE0 and DE1 of the SSCON register are cleared returns the data in the register
to the CPU without generating a receive transaction on the SSI.
It is possible to support multiple devices connected to the SSI bus simultaneously. In one
scenario, it may be possible to connect all the devices to the SDEN signal and develop a
software protocol to manage individual device communication.
Alternatively, PIO signals can serve as external device enables in addition to the provided
SDEN signal. In this scenario, to communicate to one of the devices using a PIO as an SSI
enable signal, software must configure the pin as a PIO output, force the PIO to be asserted,
and then set the synchronous serial data enable bit (DE1) in the SSCON register. Setting
this bit and asserting the PIO enables the external device to which this PIO signal is
connected for communication on the SSI and writing the SSTXDx register or reading the
register initiates a data transfer. For a receive operation, reading the SSRXD register when
the DE1 and the DE0 bits are cleared returns the data in the receive register to the CPU
without causing a receive transaction to be generated on the SSI. Note that the DE0 and
DE1 bits can be set simultaneously to achieve proper receive/transmit operation.
14.5.3.4
SSI Transactions
In general, the SSI hardware provides software with a polled I/O mechanism to control its
operation. In addition to the transmit register, the receive register, and the control register,
one status register is provided. The SSI Mode/Status (SSSTAT) register provides software
with “busy”, “receive/transmit end”, and “error” status. These bits are called PB (busy), DR/
DT (receive/transmit end), and RE/TE (error). A write to either SSTXD1 or SSTXD0, or a
read to SSRXD while PB=1, sets the RE/TE bit and does not generate additional data
transfers.
For SSI transmit and receive transaction examples, see Figure 14-3–Figure 14-5.
Содержание Am186 CC
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Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...