System Overview
Am186™CC/CH/CU Microcontrollers User’s Manual
3-11
BHE
[PIO34]
{ADEN}
O
Bus High Enable: During a memory access, BHE and the least-
significant address bit (AD0) indicate to the system which bytes
of the data bus (upper, lower, or both) participate in a bus cycle.
The BHE and AD0 pins are encoded as follows:
BHE is asserted during t
1
and remains asserted through t
3
and
t
W
. BHE does not require latching. BHE is three-stated with a
pullup during bus-hold and reset conditions.
WLB and WHB implement the functionality of BHE and AD0 for
high and low byte write enables, and they have timing
appropriate for use with the nonmultiplexed bus interface.
BHE also signals DRAM refresh cycles when using the
multiplexed address and data (AD) bus. A refresh cycle is
indicated when both BHE and AD0 are High. During refresh
cycles, the AD bus is driven during the t
1
phase and three-stated
during the t
2
, t
3
, and t
4
phases. The value driven on the A bus
is undefined during a refresh cycle. For this reason, the A0 signal
cannot be used in place of the AD0 signal to determine refresh
cycles.
BSIZE8
—
O
Bus Size 8 is asserted during t
1
–t
4
to indicate an 8-bit cycle, or
is deasserted to indicate a 16-bit cycle.
DEN
[DS]
[PIO30]
O
Data Enable supplies an output enable to an external data-bus
transceiver. DEN is asserted during memory and I/O cycles.
DEN is deasserted when DT/R changes state. DEN is three-
stated with a pullup during bus-hold or reset conditions.
[DRQ0]
DRQ1
PIO9
—
STI
STI
DMA Requests 0 and 1 indicate to the microcontroller that an
external device is ready for a DMA channel to perform a transfer.
DRQ1–[DRQ0] are level-triggered and internally synchronized.
DRQ1–[DRQ0] are not latched and must remain active until
serviced.
Table 3-7
Signal Descriptions (Continued)
Signal Name
1
Multiplexed
Signal(s)
Type Description
Data Byte Encoding
BHE
AD0
Type of Bus Cycle
0
0
Word transfer
0
1
High byte transfer (bits
15–8)
1
0
Low byte transfer (bits
7–0)
1
1
Refresh
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...