DRAM Controller
Am186™CC/CH/CU Microcontrollers User’s Manual
6-3
6.4
REGISTERS
Table 6-2 lists the 16-bit peripheral registers that determine the operation of the DRAM
controller. You must also program the LDEN bit of the LMCS register and the UDEN bit of
the UMCS register for DRAM operation. Appendix A summarizes the bits in all the registers.
For a complete description of all the peripheral registers, see the
Am186™CC/CH/CU
Microcontrollers Register Set Manual, order #21916.
6.5
OPERATION
6.5.1
Usage
Note: Before using the DRAM controller, ensure the multiplexed pins listed in Table 6-1 on
page 6-2 (PIOs, chip selects, and DRAM) are configured to reflect the use of the DRAM
controller and not other functionality.
To enable DRAM support for the Am186CC/CH/CU microcontrollers, use the following
process:
1. Configure the UCS or LCS chip selects for DRAM. For information, see “Selecting DRAM
Using the Chip Selects” on page 5-7.
2. Set the RC bit field in the CDRAM register to the DRAM refresh rate. This is the number
of CPU clocks between refresh cycles. All refresh cycles contain three wait states to
accommodate the various DRAMs supported. Note that changing the value of this field
after DRAM refresh has been enabled does not load the new value into the refresh
counter until the current counter value has reached 0.
3. Set the EN bit of the EDRAM register to 1 to enable DRAM refresh.
6.5.2
DRAM Supported
The Am186CC/CH/CU microcontrollers support one or two banks of 40-ns, 50-ns, 60-ns,
or 70-ns, 4-Mbit (256 Kbit x 16 bit), symmetrical Extended Data Out (EDO) DRAM (EDO
DRAM is sometimes called Hyper-Page Mode DRAM).
Eight-bit (byte-wide) DRAM is not supported, and the DRAM does not operate properly if
configured as an 8-bit area. However, it is still possible to perform byte accesses to 16-bit
DRAM. Simply perform a 16-bit read and choose the upper or lower byte as needed.
The Am186CC/CH/CU microcontrollers can boot from a nonvolatile memory device in UCS
space and later switch the UCS space to a DRAM. The microcontrollers also support an
8-bit UCS boot mode, which allows the user to boot from an 8-bit device and later switch
to 16-bit operation. It is not possible to boot from a 16-bit memory device and later switch
to an 8-bit device. See Chapter 5, “Chip Selects,” for details.
Table 6-3 shows the wait states used to support DRAM.
Table 6-2
DRAM Controller Register Summary
Offset
Register
Mnemonic
Register Name
Description
3AAh
CDRAM
Refresh Clock Prescaler
Used to configure the DRAM refresh rate.
3ACh
EDRAM
Enable Refresh Control
Used to enable the refresh counter. It can also
be used to sample the present value of the
refresh down counter.
Содержание Am186 CC
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Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
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Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...