Glossary
Am186™CC/CH/CU Microcontrollers User’s Manual
Glossary-5
interrupt transfer
One of four USB transfer types. Interrupt transfers have
the following characteristics: small data, nonperiodic,
low frequency, and bounded latency. They are device-
initiated communications typically used to notify the
host of device service needs.
interrupt type
An eight-bit number assigned to each discrete interrupt
(see Table 7-3 on page 7-12). Each interrupt type does
not need a unique interrupt channel; one interrupt chan-
nel can support more than one interrupt type. However,
if two interrupt types are supported by one channel,
then those two types have the same level of program-
mable priority.
interrupt vector address
Equals the interrupt type times four and is the location
in the interrupt vector table that stores the address of
the interrupt service routine for each interrupt type.
interrupt vector table
A memory area of 1 Kbyte beginning at address 00h
that contains up to 256 four-byte interrupt vector
addresses.
IOM-2
ISDN-oriented modular interface, revision 2.
See
GCI.
ISDN
Integrated services digital network. A telecommunica-
tions network that allows for digital voice, video, and
data transmissions. ISDN replaces the analog tele-
phone system with a fast and efficient digital
communications network. ISDN lines contain two chan-
nels: a B channel, which has a 64-Kbit/s data
transmission rate, and a D channel, which has either a
16-Kbit/s or 64-Kbit/s transmission rate. When the two
lines are used together, transmitted data can travel at
128 Kbit/s.
isochronous transmission
A data transmission process in which there is always an
integral number of unit intervals between any two signif-
icant instants.
Compare to
synchronous transmission
and
asynchronous transmission.
isochronous transfer
One of four USB transfer types. Isochronous transfers
are used when working with isochronous data. Isochro-
nous transfers provide periodic, continuous
communication between host and device.
ISR
Interrupt service routine. The software executed when
the interrupt processing unit receives an interrupt
request. The interrupt vector points to this code.
L
LANCE
Local area network controller for ethernet.
LAP-B
Link access procedure, balanced.
LAP-D
Link access procedure, D channel.
latency
A time period for an event to cause another event.
See
also
interrupt latency
,
DMA latency
, and
HOLD latency.
LSB
Least significant bit.
M
maskable interrupt
An interrupt that can be enabled (unmasked) or dis-
abled (masked) by setting or clearing a bit in the
appropriate mask register. Maskable interrupts as a
group are enabled and disabled by setting or clearing
the Interrupt-Enable Flag (IF) in the Processor Status
Flags (FLAGS) register. Nonmaskable interrupts are not
affected by this bit setting.
message pipe
A pipe that transfers data using a request/data/status
paradigm. The data has an imposed structure that
allows requests to be reliably identified and
communicated.
MSB
Most significant bit.
multidrop
A communication configuration in which more than two
stations share a transmission path. A typical multidrop
configuration has a number of secondary devices (e.g.,
terminals) and a primary device (e.g., host computer) on
the same path or line.
multiplexed mode
The connection of an HDLC channel to an external
interface through a TSA. In multiplexed mode, an HDLC
channel can be connected to a PCM highway or GCI
interface.
Compare to
nonmultiplexed mode.
multiplexed signal
A signal that shares a pin with at least one other signal.
multipoint
See
multidrop.
mux
Abbreviation for multiplexer.
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...