High-Level Data Link Control (HDLC)
15-12
Am186™CC/CH/CU Microcontrollers User’s Manual
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Abort Generation: The HDLC transmitter sends an abort sequence (one 0 followed by
seven to 14 1s) whenever the FORABR bit of the HxTCON0 register is set to 1. The
transmitter continues sending an abort sequence as long as this bit is set; however, if
the send abort bit is set and cleared on two successive writes to the HDLC Command/
Control register, at least one abort character is sent. An abort is also sent if CTS is lost
while the transmitter is in-frame (and CTS is enabled) or if a transmit FIFO underflow
occurs (unless in Transparent mode). When in GCI (Am186CC microcontroller only) or
multidrop mode, only one abort is sent and then the transmitter is turned off.
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Parallel-to-Serial Shift Register: The HDLC transmitter loads the output of the transmit
FIFO or the flag/abort generator one byte at a time into the parallel-to-serial shift register
and then shifts it out. Transmission of a flag or abort sequence bypasses the zero-bit-
insertion logic.
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CRC Generator: The CRC or Frame Check Sequence (FCS) contains the generated
CRC code for the frame being transmitted. All data transmitted between the opening
and closing flags (excluding inserted 0s) is included in the CRC calculation. The
transmitter appends the calculated CRC to the end of the frame just before the closing
flag. The transmitter supports the CRC-CCITT, CRC-16, and CRC-32 algorithms,
selected in the CRCTYPE field of the HxCON register. You can disable CRC generation
by setting the CRCDIS bit of the HxTCON0 register to 1. When CRC is disabled, the
transmitter does not append the CRC bytes to the end of the frame. The disable option
may be changed at any time before the last byte is to be transmitted. This ability allows
programmed I/O to generate some frames with CRC and some without CRC.
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Zero-Bit lnsertion: The zero-bit-insertion logic, also referred to as data transparency,
ensures that the remote receiver does not recognize a flag, mark-idle, or abort embedded
in the data. The zero-bit-insertion logic monitors the data stream between the opening
and closing flags of a frame and inserts a 0 after detecting five contiguous 1s. Zero-bit
insertion does not operate in Transparent mode or when generating flags, mark-idles,
or aborts.
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Transmit Enable: When transmit is disabled, the transmitter waits for the current frame
to complete transmission (if there is one) and for status on that frame to be reported,
then sets the transmitter stopped bit and begins transmitting either flags or marks
depending on the selected idle condition. While transmit is disabled, the transmitter
continues to fill up its internal pipe and FIFO. If the transmit FIFO contains data when
transmit is enabled, the transmitter begins transmission within one bit time of when
external CTS is asserted. If the idle condition is flag-idle, the transmitter finishes the
current flag before starting transmission of data. If the idle condition is mark-idle and at
least 16 1s have been transmitted, the transmitter may not finish the current mark idle
sequence before starting data transmission. To disable transmit, clear the HTEN bit of
the HxTCON0 register.
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Transmit-FIFO Enable: Normal operation requires both the Transmit Enable (HTEN)
and the Transmit FIFO Enable (TFIFOEN) bits of the HxTCON0 register to be set.
Clearing the TFIFOEN bit causes the transmit FIFO data to be flushed. To avoid possible
data loss, disable SmartDMA control before flushing the FIFO.
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Output States: The serial data output pin on the DCE interface (DCE_TXD_x) supports
three-state (reset default), open drain, or totem pole operation under program control.
The output must be set to open drain for proper operation in multidrop mode. Specify
the output state in the ODRV field of the HxTCON1 register.
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Transmitter Status: After transmitting a frame, the transmitter generates a maskable
interrupt. If an error occurs during transmission, the transmitter stops. Read the
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...