Synchronous Serial Port (SSI)
Am186™CC/CH/CU Microcontrollers User’s Manual
14-5
the falling edge of the SCLK signal and is received (latched into the microcontroller) on the
rising edge of the SCLK signal. In the Inverted Clock mode, data is transmitted on the
SDATA pin on the rising edge of the SCLK signal and is received (latched into the
microcontroller) on the falling edge of the SCLK signal.
When no transmit or receive transaction is active on the SSI, the SDATA signal is three-
stated (although it has a weak keeper to hold the last value driven on the SDATA signal).
When data is transmitted on the SSI from the microcontroller to another device, the SDATA
signal is driven and is stable after the falling edge (rising edge if in the Inverted Clock mode)
of the SCLK signal, providing the appropriate setup and hold time for the receiving device
if that device latches this data on the rising edge (falling edge in the Inverted Clock mode)
of SCLK.
14.5.3.2
SDATA
When the microcontroller receives data from another device on the SSI, it latches the level
driven onto the SDATA signal by the transmitting device on the rising edge (falling edge if
in the inverted clock mode) of the SCLK signal. The transmitting device must meet the
required setup and hold times relative to this SCLK rising edge (falling edge if in the inverted
clock mode).
Software writes data to be transmitted on the SSI by the microcontroller to either of the two
SSI transmit registers (SSTXD0 or SSTXD1). The transmit registers are 16-bit registers
but only the lower eight bits can be written and the upper eight bits are ignored. When a
new value is written to one of the transmit registers, and software has previously enabled
SSI and the external device (see the description of the SDEN signal below), the SSI shifts
out the data written to the transmit register on SDATA.
To receive data from an external device, the microcontroller must initiate the receive
transaction by toggling the SCLK signal and sampling the SDATA input. A receive
transaction is initiated if the external device has been enabled (see the description of the
SDEN signal below) and software reads the SSI Receive Data (SSRXD) register. The
SSRXD register is a 16-bit register but only the lower eight bits contain valid data. If the
external device is enabled, reading the SSRXD register causes the SCLK signal to be
toggled, generating eight Low-to-High transitions (High-to-Low transitions if in the Inverted
Clock mode), and the level on the SDATA signal is latched eight times and stored in the
receive register bits. Note that the initial data read (activating the read cycle) should be
discarded.
The SSI data order is configurable with the MSBF bit in the SSCON register. Two modes
are available: Normal (LSB first) and Reverse (MSB first). A single configuration bit selects
the mode and the selected mode is common for transmit and receive operations.
In Normal mode, the least significant bit (LSB) of the transmit data byte is shifted out first.
For a receive operation, the SSI stores the first data bit received in the LSB of the receive
register and stores the last data bit received in the most significant bit (MSB) of the receive
register.
In Reverse mode, the most significant bit (MSB) of the transmit data byte is shifted out first.
For a receive operation, the SSI stores the first data bit received in the MSB of the receive
register and stores the last data bit received in the LSB of the receive register.
14.5.3.3
SDEN
The SDEN signal enables an external device for communication on the SSI bus. The
microcontroller asserts this signal, under software control, before it initiates the transmit or
receive operation to or from a device on the SSI. The DE0 bit controls the state of this
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...