Glossary
Glossary-6
Am186™CC/CH/CU Microcontrollers User’s Manual
N
NACK
Negative acknowledgment.
nibble
Half a byte (four bits).
NMI
Nonmaskable interrupt. An interrupt that cannot be dis-
abled (masked).
nonmultiplexed mode
The connection of an HDLC channel directly to an exter-
nal interface without going through a TSA. In
nonmultiplexed mode, an HDLC channel can be con-
nected to a raw DCE interface.
Compare to
multiplexed
mode.
NRZ
Non-return to zero.
NRZI
Non-return to zero, inverted.
O
odd parity
See
parity.
ONCE
On-circuit emulation.
OSI
Open systems interconnection. An ISO standard for
worldwide communications that defines a framework for
implementing protocols in seven layers. Control is
passed from one layer to the next.
overall priority
Each interrupt source has an overall priority number
that is used only to arbitrate between two interrupt
sources that have priority requests pending with the
same programmable priority level. Overall priority is not
used if the programmable priority is sufficient to resolve
the pending highest-priority request.
P
PABX
Private automatic branch exchange.
packet
A self-contained message unit transmitted through a
communications network. Typically, the transmitter
breaks a longer message into packets to avoid the net-
work performance degradation caused by long
messages. A packet contains three parts: control infor-
mation (source, destination address, length), the data to
be transmitted, and error detection and correction bits.
A packet may be made up of one or more frames.
packet buffer
The logical buffer used by a USB device for sending or
receiving a single packet. This determines the maxi-
mum packet size the device can send or receive.
packet ID
A field in a USB packet that indicates the type of packet,
and by inference the format of the packet and the type
of error detection applied to the packet.
parity
An error-checking procedure for checking the accuracy
of serial data streams based on whether the number of
1 bits is even or odd. A parity bit is added to each group
of data bits in a transmission. In
even parity
, the parity
bit is set to 1 whenever it is needed to bring the total
number of 1 bits to an even number. In
odd parity
, the
parity bit is set to 1 whenever it is needed to bring the
total number of 1 bits to an odd number.
PCB
Peripheral control block. Each 16-bit read/write periph-
eral register is in the internal 1-Kbyte peripheral control
block (PCB). Registers are physically located in the
peripheral devices they control, but they are addressed
as a single 1-Kbyte block. This block is located in either
memory or I/O space, at the location pointed to by the
Peripheral Control Block Relocation (RELOC) register.
Because the base address of the block can change, the
address of each register is specified as an offset from
the RELOC register, rather than as an absolute
address. The register address is found by adding the
offset to the base address to determine the physical
location in memory or I/O space.
The PCB base address can be set to any even 1-Kbyte
boundary in memory or I/O space (i.e., the lower 10 bits
of the base address must be 0). The RELOC register
resides in the last register address of the PCB, at offset
03FEh. At reset, the base of the PCB is set to FC00h in
I/O space. This places the RELOC register at FFFEh.
PCM
Pulse code modulation. A technique for converting ana-
log signals into digital form that is widely used by the
telephone companies in their T1 circuits. In North Amer-
ica and Japan, PCM samples the analog waves 8,000
times per second and converts each sample into an 8-
bit number, resulting in a 64-Kbit/s data stream. The
sampling rate is twice the 4-KHz bandwidth required for
a toll-quality conversation.
PCM highway
Pulse code modulation highway. One of the external
interfaces supported by the Am186CC communications
controller HDLC channels.
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...