System Overview
3-10
Am186™CC/CH/CU Microcontrollers User’s Manual
Table 3-7
Signal Descriptions
Signal Name
1
Multiplexed
Signal(s)
Type Description
BUS INTERFACE/GENERAL-PURPOSE DMA REQUEST
A19–A0
—
O
Address Bus supplies nonmultiplexed memory or I/O
addresses to the system one half of a CLKOUT period earlier
than the multiplexed address and data bus (AD15–AD0). During
bus-hold or reset conditions, the address bus is three-stated with
pulldowns.
When the lower or upper chip-select regions are configured for
DRAM mode, the A19–A0 bus provides the row and column
addresses at the appropriate times. The upper and lower
memory chip-select ranges can be individually configured for
DRAM mode.
AD15–AD0
—
B
Address and Data Bus time-multiplexed pins supply memory
or I/O addresses and data to the system. This bus can supply
an address to the system during the first period of a bus cycle
(t
1
). It transmits (write cycle) or receives (read cycle) data to or
from the system during the remaining periods of that cycle (t2,
t3, and t4). The address phase of these pins can be disabled—
see the {ADEN} pin description in Table 3-5 on page 3-7.
During a reset condition, the address and data bus is three-
stated with pulldowns, and during a bus hold it is three-stated.
In addition, during a reset the state of the address and data bus
pins (AD15–AD0) is latched into the Reset Configuration
(RESCON) register. This feature can be used to provide software
with information about the external system at reset time.
ALE
[PIO33]
O
Address Latch Enable indicates to the system that an address
appears on the address and data bus (AD15–AD0). The address
is guaranteed valid on the falling edge of ALE.
ALE is three-stated and has a pulldown resistor during bus-hold
or reset conditions.
ARDY
[PIO8]
STI
Asynchronous Ready is a true asynchronous ready that
indicates to the microcontroller that the addressed memory
space or I/O device will complete a data transfer. The ARDY pin
is asynchronous to CLKOUT and is active High. To guarantee
the number of wait states inserted, ARDY or SRDY must be
synchronized to CLKOUT. If the falling edge of ARDY is not
synchronized to CLKOUT as specified, an additional clock period
can be added.
To always assert the ready condition to the microcontroller, tie
ARDY and SRDY High. If the system does not use ARDY, tie the
pin Low to yield control to SRDY.
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...