Universal Serial Bus (USB)
18-22
Am186™CC/CH/CU Microcontrollers User’s Manual
18.5.6.5
Error Recovery on Bulk and Interrupt Endpoints
When an endpoint is configured as a bulk or interrupt endpoint, data delivered over the
endpoint is guaranteed to be correct, but is not guaranteed to be delivered within any certain
time interval. When DMA is used, device software must intervene when exceptions occur
to guarantee correct data. The following error recovery situations must be considered:
■
SmartDMA channel receive does not require any low-level software intervention if the
USB DMA mode is set to 110 (store status in SmartDMA channel FIFO). Instead, the
higher level software that pulls packets out of the SmartDMA channel FIFO descriptor
ring must examine each FIFO’s status to determine if it was received correctly or not,
and discard FIFOs with errors.
■
If SmartDMA channel receive is used when the USB DMA mode is set to 100 (don’t
store status), then all status processing must be performed by low level software. This
mode is typically used for bulk data if it is desired to receive an entire USB IRP as a
single FIFO. Because the USB hardware is not storing any status in the SmartDMA
channel descriptors, it is up to software to program the USB endpoint to interrupt
whenever an error or a short packet is received. The interrupt handler should then disable
the SmartDMA channel, update the SmartDMA channel descriptor (because some good
data may have been stored before the bad data—the descriptor is updated to point to
where the bad data was received so that it can be overwritten) and the SmartDMA
channel descriptor pointer, re-enable the SmartDMA channel, and then restart the USB
endpoint by clearing the ACT_REQ and interrupt bits. This is a significant amount of
overhead, but the interrupt routine is only executed when an error or an end of packet
occurs, and the higher level software never needs to worry about retrieving bad data
from the FIFO, because the interrupt routine can make sure that all stored data is good
before status is stored.
■
Like SmartDMA channel receive, general-purpose DMA receive can either be performed
per packet or per IRP, depending on whether the USB is programmed to stop on all
packets or just on short packets. If an error occurs, it is up to the software to back the
DMA pointer up to the start of the current packet (using information about where it is
and how much data is still left in the FIFO), and clear the error and the ACT_REQ bit.
■
SmartDMA channel transmit requires the USB to be set to stop on errors. If an error
occurs during transmit, the interrupt handler must disable the SmartDMA channel,
program its FIFO pointer to point back to the failing location, restart the DMA, and then
flush the FIFO and restart the endpoint by clearing the ACT_REQ, NOT_FLUSH, and
error bits. If the SmartDMA channel is being used in buffer-per-packet mode, then only
the SmartDMA channel’s FIFO descriptor pointer needs to be updated, but if the
SmartDMA channel is being used in a buffer-per-IRP mode, then the SmartDMA
channel’s memory pointer must be read, and the actual FIFO descriptor in memory must
be reprogrammed (starting address and length) so that the DMA can be restarted in the
middle of the FIFO. When reprogramming the starting address, the number of bytes that
were transferred from memory to the FIFO before the error occurred must be taken into
account.
■
General-purpose DMA transmit requires that the DMA mode be set to 011, to stop and
interrupt on DMA terminal count. As with the SmartDMA channel, just because a DMA
FIFO has been sent to the host doesn’t mean that it has been successfully delivered.
Interrupts should be enabled for FIFO errors and other errors, and if an error occurs, the
current packet must be resent. If multiple packets are in the FIFO (buffer per IRP), then
the start of the current packet in the FIFO must be calculated by taking into account the
current DMA pointer and the number of bytes that are currently stored in the endpoint's
FIFO. The endpoint's FIFO should be flushed before DMA is restarted.
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...