Interrupts
7-6
Am186™CC/CH/CU Microcontrollers User’s Manual
7.5
OPERATION
7.5.1
Usage
Note: Before using the interrupts, ensure multiplexed signals are configured to reflect the
use of the interrupts and not other functionality (see Table 7-1 on page 7-4).
7.5.1.1
Types of Interrupt Channels
The interrupt channels can be organized into five groups: Channel 0 (timers), Channel 1
(INT0 only), channels which support both an external and internal source (Channels 2, 3,
and 8–13), channels which support two internal sources (Channels 4–7), and Channel 14
(shared interrupts). Channel 1 is a straightforward, single interrupt channel. For a list of
interrupt types, see Table 7-3 on page 7-12. For a map of the interrupt channels, see
Table 7-4 on page 7-16. The following sections discuss the other groups.
7.5.1.1.1
Timer Interrupt Requests Channel
Interrupt Channel 0 supports the three timers. Each timer has a bit in its control register
that determines whether it is enabled to generate interrupt requests to the channel. The
timers share a single programmable priority set in the CH0CON register. In addition, the
three timers have relative priorities (see Table 7-3 on page 7-12). The Interrupt Controller
uses the relative priority to arbitrate between the timers when more than one has an interrupt
request pending. The channel logic determines which of the sources has the highest priority
pending request and generates the interrupt vector based on that request. In previous parts,
it could be confusing that all three interrupts required the same EOI (that of TMR0) even
though they had different vectors. This happened because for all other sources, the vector
number was identical with the EOI type. In the Am186CC/CH/CU microcontrollers, any of
the three vector numbers can be used for the EOI; however, all three function identically by
clearing the in-service bit for Channel 0. Table 7-3 on page 7-12 lists the EOI type for each
interrupt.
Channel 9 (supports general-purpose DMA0 and general-purpose DMA1 as well as INT4)
and Channel 10 (supports general-purpose DMA2 and general-purpose DMA3 as well as
INT5) have similar behavior to the timers in regard to their support of the two DMA channels.
7.5.1.1.2
External and Internal Interrupt Request Channels
At any given point in time, interrupt channels 2, 3, 8, 9, 10, 11, 12, and 13 all support either
an external or an internal source, but not both. The SRC bit in the CHxCON register
determines the source for Channels 2, 3, and 8–11. Channels 12 and 13 support the
external source until the PWD bit in the SYSCON register is set. For example, Channel 2
services the USB when the SRC bit is set, or INT1 when the SRC bit is cleared. The setting
332h
SHREQ
Interrupt Shared Request
Indicates if an INT signal that is enabled for
shared interrupts is currently requesting an
interrupt on the shared channel, Channel 14.
334h
SHMASK
Interrupt Shared Mask
Determines if an INT signal is masked
(disabled) as a source for Channel 14.
336h
INTPOL
Interrupt Polarity
Sets the polarity, active High or active Low, of
the INT signals.
338h
PIOPOL
PIO Polarity
Sets the polarity, active High or active Low, of
the eight PIO signals that can be configured as
interrupt sources.
Table 7-2
Interrupt Controller Register Summary (Continued)
Offset
Register
Mnemonic
Register Name
Description
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