Interrupts
Am186™CC/CH/CU Microcontrollers User’s Manual
7-15
The interrupt controller uses the peripheral registers listed in Table 7-2 on page 7-5 to
support generating a maskable interrupt. In addition, the FLAGS processor register contains
a flag to enable the interrupts and one to set the trace interrupt. For more information about
the interrupt registers, see “Registers Used” on page 7-18.
Of the maskable interrupts, 17 signals are provided for external interrupt sources: 9 interrupt
signals and 8 PIOs (the NMI signal is
nonmaskable and is generally used for unusual events
like power failure). The interrupt types for these inputs are generated internally. Every
interrupt channel has an in-service bit. If a lower-priority device requests an interrupt while
the in-service bit (IS) is set for a high-priority interrupt, the interrupt controller does not
generate an interrupt. In addition, if another interrupt request occurs from the same interrupt
source while the in-service bit is set, the interrupt controller does not generate an interrupt.
This allows interrupt service routines operating with interrupts enabled to be suspended
only by interrupts of equal or higher priority than the in-service interrupt.
When an interrupt service routine completes, software must reset the proper in-service bit
by writing the EOI type to the EOI register. This is required to allow subsequent interrupts
from this interrupt source and to allow servicing of lower-priority interrupts. Software should
execute a write to the EOI register at the end of the interrupt service routine just before the
return from interrupt instruction.
7.5.5.5
Maskable Interrupt Block Diagram
Figure 7-3 shows a partial block diagram of how the sources and channels are used (see
Figure 7-1 on page 7-3 for another block diagram). The three timers share Channel 0 and
produce three separate types. The INT0 signal is dedicated to Channel 1. The GP DMA0
and GP DMA1 are MUXed with the INT4 signal onto Channel 9, and they produce up to
two separate types (only one type is generated if Channel 9 services the INT4 signal). The
INT4 signal is also connected to the Channel 14 shared interrupts through a mask register
and shares the same type as the rest of the Channel 14 shared interrupts.
Figure 7-3
Partial Block Diagram of Interrupt Controller Scheme
15 Interrupt Channels
3 Types
CH0
INT4
GP DMA1
GP DMA0
CH9
CH14
2 Types
8 PIOs
INT1-3,5-7
1 Shared Type
CH1
INT0
TIM0
TIM1
TIM2
1 Type
MASK
CH1
Содержание Am186 CC
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Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
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Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...