Chip Selects
5-10
Am186™CC/CH/CU Microcontrollers User’s Manual
5.5.6
Programming Ready Signals and Wait States
The Am186CC/CH/CU microcontrollers can sense a ready signal for each of the peripheral
or memory chip select lines. The ready signal can be either the ARDY or SRDY signal.
Each chip select control register (UMCS, LMCS, PACS, MMCS, and MPCS) contains a
single-bit field, R2, that determines whether the external ready signal is required or ignored.
When R2 is set to 1, external ready is ignored. When R2 is cleared to 0, external ready is
required.
The number of wait states to be inserted for each access to a peripheral or memory region
is programmable. 0–3, 5, 7, 9, or 15 wait states can be inserted for the PCS7–PCS4
peripheral chip selects.
Note: Because of how the DRAM access is terminated, it is illegal to allocate a PCS space
with fewer wait states than the DRAM it is overlapping.
Zero to three wait states can be inserted for all other chip selects. Two bits, R1 and R0, in
each of the chip select control registers program the wait states. The PACS register also
has the R3 bit for the additional PCS wait states.
When external ready is required (R2 is 0), internally programmed wait states always
complete before external ready terminates or extends a bus cycle. For example, if the
internal wait states are set to insert two wait states (R1–R0 = 10b), the processor samples
the external ready signal during the first wait cycle. If external ready is asserted at that time,
the access completes after six cycles (four cycles plus two wait states). If external ready is
not asserted during the first wait cycle, the access is extended until ready is asserted, which
is followed by one more wait state followed by t
4
.
When external readys are ignored (R2 is 1), the R1 and R0 bits alone configure the number
of wait states. If DRAM is enabled for UCS or LCS, external readys are ignored regardless
of the setting of R2.
The ARDY signal on the Am186CC/CH/CU microcontrollers is a true asynchronous ready
signal. The ARDY signal accepts a rising edge that is asynchronous to CLKOUT and is
active High. If the falling edge of ARDY is not synchronized to CLKOUT as specified, an
additional clock period may be added.
5.5.7
Chip Select Timing
The timing for the UCS and LCS outputs has been modified from the original 80C186
microcontroller. These outputs now assert with the nonmultiplexed address bus (A19–A0)
for normal memory timing. To allow these outputs to be available earlier in the bus cycle,
the number of programmable memory size selections has been reduced.
The MCS and PCS chip selects assert with the AD bus.
For more information about chip select timing, see the data sheets for the Am186CC/CH/
CU microcontrollers.
5.5.8
Hardware-Related Considerations
■
The LCS memory space supports use of either the DRAM interface or the SRAM
interface, not both.
5.5.9
Software-Related Considerations
■
The chip selects are activated only by a write to a register. Chip selects on previous
Am186 devices activated with a read or a write.
■
The UMCS, LMCS, and MPCS registers contain a new data bus width bit; therefore,
legacy code may accidentally change the bus width when writing to these registers.
Содержание Am186 CC
Страница 1: ...Am186 CC CH CU Microcontrollers User s Manual Order 21914B...
Страница 4: ...iv Am186 CC CH CU Microcontrollers User s Manual...
Страница 18: ...Table of Contents xviii Am186 CC CH CU Microcontrollers User s Manual...
Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
Страница 39: ...Architectural Overview Am186 CC CH CU Microcontrollers User s Manual 1 15 Figure 1 6 32 Channel Linecard CH CC...
Страница 40: ...Architectural Overview 1 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 86: ...System Overview 3 36 Am186 CC CH CU Microcontrollers User s Manual...
Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...