Interrupts
7-14
Am186™CC/CH/CU Microcontrollers User’s Manual
7.5.5.2
Interrupts In Polled Mode
Software can handle interrupt requests in polled mode. In polled mode, configure the
interrupt sources exactly as in normal interrupt mode, but do not set the IF bit in the FLAGS
register. This disables automatic hardware servicing of interrupt requests. In this case,
software must periodically read the POLL or POLLST register to determine if a valid interrupt
request is pending. Reading the POLL or POLLST register provides identical information;
however, a read of the POLL register generates an interrupt recognition cycle whereas a
read of the POLLST register does not.
Except for the manner in which the interrupt recognition is generated, and the fact that
software must jump to the interrupt service routine, the behavior under normal interrupt
and polled mode interrupt is identical. This means, for example, that the CHx bit in the
INSVR register must be cleared by an EOI instruction as in normal interrupt mode.
7.5.5.3
Considerations for NMI, Software Interrupts, and Traps
The nonmaskable interrupt (NMI) is not processed through the interrupt controller. Its
detection is not affected by the settings of the IF flag, the bits in the INSRV register, or by
the priority mask. When an NMI interrupt is taken, the IF flag is cleared and the DHLT bit
is set. This disables maskable interrupts and inhibits DMA transfers.
Although the NMI is the highest priority hardware interrupt, it does not participate in the
priority resolution scheme of the maskable interrupts. Setting the IF flag using the STI
instruction during an NMI service routine is discouraged because any maskable interrupt
may interrupt an executing NMI routine, assuming it meets the criteria outlined above. DMA
activity may be re-enabled by clearing the DHLT bit but this could increase the number of
cycles required to complete the NMI routine and, consequently, the number of cycles during
which interrupts are disabled.
A currently executing NMI service routine may be preempted by a second NMI request.
NMI is active when the part is reset and cannot be disabled.
The NMI can be generated externally through the NMI pin or internally through the watchdog
timer. The microcontroller logically ORs the two sources internally to provide a single signal
to the execution unit. Because the NMI signal is edge-sensitive, it is possible to block the
recognition of a watchdog timer NMI by holding the external NMI signal asserted. Systems
that do not use external NMI should hold this pin low to yield control to the watchdog timer
NMI.
A software interrupt or trap is not processed through the interrupt controller and is not
affected by the setting of the IF flag, the bits in the INSRV register, by the priority mask, or
by a currently executing NMI service routine.
7.5.5.4
Maskable Interrupt Overview
Interrupt types 08h through 1Eh are maskable (see Table 7-3 on page 7-12). The maskable
interrupts are enabled and disabled by the IF flag in the FLAGS register, but the INT
command can execute any interrupt regardless of the setting of IF.
Maskable interrupts are supported through the interrupt controller, which contains the
configuration and status of all the interrupt sources, as well as priority resolution logic to
select which interrupts to process in which order. The interrupt controller supports maskable
interrupts with 15 interrupt channels. Because of the large number of interrupt sources
available, some sources share interrupt channels. Table 7-4 on page 7-16 and Table 7-5
on page 7-17 show which channels service each source.
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Страница 24: ...Introduction xxiv Am186 CC CH CU Microcontrollers User s Manual...
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Страница 92: ...Emulator Support 4 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 112: ...DRAM Controller 6 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 134: ...Interrupts 7 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 186: ...Programmable I O Signals 9 8 Am186 CC CH CU Microcontrollers User s Manual...
Страница 200: ...Watchdog Timer 11 6 Am186 CC CH CU Microcontrollers User s Manual...
Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
Страница 348: ...Register Summary A 16 Am186 CC CH CU Microcontrollers User s Manual...
Страница 376: ...Index Index 18 Am186 CC CH CU Microcontrollers User s Manual...