Interrupts
Am186™CC/CH/CU Microcontrollers User’s Manual
7-19
7.5.6.1
Software Interrupts
Up to 256 possible interrupts can be initiated by the INT or INTO instructions. INT 21h
causes an interrupt to the vector located at 00084h in the interrupt vector table. INT FFh
causes an interrupt to the vector located at 003FCh in the interrupt vector table.
7.5.6.2
Divide Error Exception (Interrupt Type 00h)
When a DIV or IDIV instruction quotient cannot be expressed in the number of destination
bits, it generates a Divide Error exception.
7.5.6.3
Trace Interrupt (Interrupt Type 01h)
If the Trace Flag (TF) in the FLAGS register is set, the trace interrupt is generated after
most instructions. The trace interrupt is the highest priority interrupt. This interrupt allows
programs to execute in single-step mode. The interrupt is not generated after prefix
instructions like REP, instructions that modify segment registers like POP DS, or the WAIT
instruction.
Taking the trace interrupt clears the TF bit after the flags are pushed onto the stack. The
IRET instruction at the end of the single step interrupt service routine restores the processor
status flags (including the TF bit) and transfers control to the next instruction to be traced.
Taking the trace interrupt also clears the IF flag.
Trace mode is initiated by pushing the FLAGS register onto the stack, then setting the TF
flag on the stack, and then popping the flags.
For more information about the FLAGS register, see Chapter 2, “Configuration Basics.”
7.5.6.4
Nonmaskable Interrupt (Interrupt Type 02h)
An NMI can be generated internally or externally. An internal NMI is generated with the
watchdog timer. For more information about the watchdog timer, see Chapter 11,
“Watchdog Timer.”
An external NMI is generated with the NMI signal. This signal indicates to the microcontroller
that an interrupt request has occurred. The NMI signal is the highest priority hardware
interrupt and, unlike the INT8–INT0 signals, cannot be masked. When NMI is asserted, the
processor transfers program execution to the location specified by the nonmaskable
interrupt vector in the interrupt vector table.
Additionally, when an NMI occurs, DMAs are suspended. If your application is using a DMA
channel, the NMI interrupt handler may need to update the DMA configuration settings to
account for the DMA being suspended by the NMI.
An NMI transition from Low to High is latched and synchronized internally, and it initiates
the interrupt at the next instruction boundary. To guarantee that the interrupt is recognized,
the NMI signal must be asserted for at least one CLKOUT period.
For information about the nonmaskable interrupt and interrupt priority processing, see
“Considerations for NMI, Software Interrupts, and Traps” on page 7-14.
7.5.6.5
Breakpoint Interrupt (Interrupt Type 03h)
The 1-byte version of the INT instruction (INT3) causes a breakpoint interrupt.
7.5.6.6
INT0 Detected Overflow Exception (Interrupt Type 04h)
If the OF bit is set in the FLAGS register, an INT0 instruction generates the INT0 Detected
Overflow exception. For more information about the FLAGS register, see Chapter 2,
“Configuration Basics.”
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Страница 232: ...Asynchronous Serial Ports UARTs 13 24 Am186 CC CH CU Microcontrollers User s Manual...
Страница 242: ...Synchronous Serial Port SSI 14 10 Am186 CC CH CU Microcontrollers User s Manual...
Страница 264: ...High Level Data Link Control HDLC 15 22 Am186 CC CH CU Microcontrollers User s Manual...
Страница 332: ...Universal Serial Bus USB 18 34 Am186 CC CH CU Microcontrollers User s Manual...
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