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8-1
AINTC Interrupt Connections
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8-2
Interrupt Controller (INTC) Registers
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8-3
Interrupt Status of INT[31:0] (if mapped to FIQ) Field Descriptions
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8-4
Interrupt Status of INT[63:32] (if mapped to FIQ) Field Descriptions
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8-5
Interrupt Status of INT[31:0] (if mapped to IRQ) Field Descriptions
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8-6
Interrupt Status of INT[31:0] (if mapped to IRQ) Field Descriptions
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8-7
Fast Interrupt Request Entry Address Register (FIQENTRY) Field Descriptions
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8-8
Interrupt Request Entry Address Register (IRQENTRY) Field Descriptions
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8-9
Interrupt Enable Register 0 (EINT0) Field Descriptions
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8-10
Interrupt Enable Register 1 (EINT1) Field Descriptions
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8-11
Interrupt Operation Control Register (INTCTL) Field Descriptions
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8-12
EABASE Field Descriptions
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8-13
Interrupt Priority Register 0 (INTPRI0) Field Descriptions
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8-14
Interrupt Priority Register 1 (INTPRI1) Field Descriptions
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8-15
Interrupt Priority Register 2 (INTPRI2) Field Descriptions
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8-16
Interrupt Priority Register 3 (INTPRI3) Field Descriptions
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8-17
Interrupt Priority Register 4 (INTPRI4) Field Descriptions
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8-18
Interrupt Priority Register 5 (INTPRI5) Field Descriptions
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8-19
Interrupt Priority Register 6 (INTPRI6) Field Descriptions
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8-20
Interrupt Priority Register 7 (INTPRI7) Field Descriptions
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9-1
Master IDs
9-2
Default Master Priorities
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9-3
System Module (SYS) Registers
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9-4
PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register Field Descriptions
...........................................
9-5
PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register Field Descriptions
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9-6
PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register Field Descriptions
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9-7
PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register Field Descriptions
..........................................
9-8
PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register Field Descriptions
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9-9
BOOTCFG - Boot Configuration Field Descriptions
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9-10
ARM_INTMUX - ARM Interrupt Mux Control Register Field Descriptions
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9-11
EDMA_EVTMUX - EDMA Event Mux Control Register Field Descriptions
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9-12
DDR_SLEW - DDR Slew Field Descriptions
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9-13
CLKOUT - CLKOUT div/out Control Field Descriptions
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9-14
DEVICE_ID - Device ID Field Descriptions
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9-15
VDAC_CONFIG - Video Dac Configuration Field Descriptions
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9-16
TIMER64_CTL - Input Control Field Descriptions
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9-17
USB_PHY_CTRL - USB PHY Control Field Descriptions
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9-18
MISC - Miscellaneous Control Field Descriptions
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9-19
MSTPRI0 - Master Priorities 0 Field Descriptions
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9-20
Master Priorities 1 (MSTPRI1) Register Field Descriptions
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9-21
VPSS_CLK_CTRL - VPSS Clock Mux Control Field Descriptions
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9-22
Deep Sleep Mode Configuration (DEEPSLEEP) Register Field Descriptions
....................................
9-23
DEBOUNCE[8] - De-bounce for GIO[n] Input Field Descriptions
..................................................
9-24
VTPIOCR - VTP IO Control Field Descriptions
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10-1
Reset Types
10-2
Reset Pins
10-3
Device Configuration
11-1
NAND UBL Descriptor
...................................................................................................
11-2
UBL Signatures and Special Modes
...................................................................................
11-3
NAND IDs Supported
11-4
MMC/SD UBL Descriptor
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SPRUFX7 – July 2008
List of Tables
11