8.4.9 Interrupt Operation Control Register (INTCTL)
INTC Registers
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The interrupt operation control register (INTCTL) is shown in
and described in
Figure 8-13. Interrupt Operation Control Register (INTCTL)
31
3
2
1
0
Reserved
IDMODE
IERAW
FERAW
R-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write, R = Read only; n = value at reset
Table 8-11. Interrupt Operation Control Register (INTCTL) Field Descriptions
Bit
Field
Value
Description
31-3
Reserved
0
Reserved
2
IDMODE
Interrupt disable mode.
0
Disable immediately.
1
Disable after ack
1
IERAW
Masked interrupt reflected in the IRQENTRY register.
0
Disable reflect.
1
Enable reflect.
0
FERAW
Masked interrupt reflect in FIQENTRY register.
0
Disable reflect.
1
Enable reflect.
Interrupt Controller
102
SPRUFX7 – July 2008