![background image](http://html.mh-extra.com/html/texas-instruments/tms320dm335/tms320dm335_user-manual_1097123054.webp)
6.6.10 Bypass Divider Register (BPDIV)
PLL Controller Register Map
www.ti.com
The bypass divider register (BPDIV) is shown in
and described in
for PLLC1 and
PLLC2. BPDIV controls the divider for SYSCLKBP. The divider for PLLC1 SYSCLKBP is fixed (cannot be
changed) to 3. The divider for PLLC2 SYSCLKBP is fixed (cannot be changed) to 8. For PLLC1 and
PLLC2, the divider must always be enabled (bit BPDEN=1).
Figure 6-12. Bypass Divider Register (BPDIV)
31
16
15
14
5
4
0
Reserved
BPDEN
Reserved
RATIO
R-0
R/W-1
R-0
R-2
LEGEND: R/W = Read/Write; R = Read only; -
n
= value after reset
Table 6-13. Bypass Divider Register (BPDIV) Field Descriptions
Bit
Field
Value
Description
31-16
Reserved
0
Reserved
15
BPDEN
Divider enable for bypass clock. This bit must always be set to 1.
0
Disable
1
Enable
14-5
Reserved
0
Reserved
4-0
RATIO
0-1Fh
Divider ratio for bypass clock
PLL Controllers (PLLCs)
54
SPRUFX7 – July 2008