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7.7.6
Module Error Clear Register 1 (mod 32-41) (MERRCR1)
.........................................................
7.7.7
Power Error Pending Register (PERRPR)
...........................................................................
7.7.8
Power Error Clear Register (PERRCR)
...............................................................................
7.7.9
External Power Control Pending Register (EPCPR)
................................................................
7.7.10
External Power Control Clear Register (EPCCR)
..................................................................
7.7.11
Power Domain Transition Command Register (PTCMD)
.........................................................
7.7.12
Power Domain Transition Status Register (PTSTAT)
.............................................................
7.7.13
Power Domain Status Register 0 (PDSTATn)
......................................................................
7.7.14
Power Domain Control n Register 0 (PDCTLn)
....................................................................
7.7.15
Module Status n Register 0-32 (MDSTATn)
........................................................................
7.7.16
Module Control n Register 0-51 (MDCTLn)
.........................................................................
8
Interrupt Controller
...................................................................................................
8.1
8.2
Interrupt Mapping
8.3
INTC Methodology
8.3.1
Interrupt Mapping
8.3.2
Interrupt Prioritization
...................................................................................................
8.3.3
Vector Table Entry Address Generation
..............................................................................
8.3.4
Clearing Interrupts
8.3.5
Enabling and Disabling Interrupts
.....................................................................................
8.4
INTC Registers
8.4.1
Fast Interrupt Request Status Register 0 (FIQ0)
....................................................................
8.4.2
Fast Interrupt Request Status Register 1 (FIQ1)
....................................................................
8.4.3
Interrupt Request Status Register 0 (IRQ0)
..........................................................................
8.4.4
Interrupt Request Status Register 1 (IRQ1)
..........................................................................
8.4.5
Fast Interrupt Request Entry Address Register (FIQENTRY)
.....................................................
8.4.6
Interrupt Request Entry Address Register (IRQENTRY)
...........................................................
8.4.7
Interrupt Enable Register 0 (EINT0)
.................................................................................
8.4.8
Interrupt Enable Register 1 (EINT1)
.................................................................................
8.4.9
Interrupt Operation Control Register (INTCTL)
....................................................................
8.4.10
EABASE
8.4.11
Interrupt Priority Register 0 (INTPRI0)
............................................................................
8.4.12
Interrupt Priority Register 1 (INTPRI1)
.............................................................................
8.4.13
Interrupt Priority Register 2 (INTPRI2)
.............................................................................
8.4.14
Interrupt Priority Register 3 (INTPRI3)
.............................................................................
8.4.15
Interrupt Priority Register 4 (INTPRI4)
.............................................................................
8.4.16
Interrupt Priority Register 5 (INTPRI5)
.............................................................................
8.4.17
Interrupt Priority Register 6 (INTPRI6)
.............................................................................
8.4.18
Interrupt Priority Register 7 (INTPRI7)
.............................................................................
9
System Control Module
...........................................................................................
9.1
Overview of the System Control Module
..............................................................................
9.2
Device Identification
9.3
Device Configuration
9.3.1
Pin Multiplexing Control
..............................................................................................
9.3.2
Device Boot Configuration Status
....................................................................................
9.4
ARM Interrupt and EDMA Event Multiplexing Control
............................................................
9.5
Special Peripheral Status and Control
.................................................................................
SPRUFX7 – July 2008
Contents
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