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6.5
PLL Configuration
6.5.1 PLL Mode and Bypass Mode
6.5.1.1
PLL Mode (PLLEN = 1)
6.5.1.2
Bypass Mode (PLLEN = 0)
6.5.2 Changing Divider / Multiplier Ratios
6.5.2.1
PLLDIVn and GO Operation
PLL Configuration
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This section describes the procedures for initializing and configuring the PLL controller.
This section describes the sequence for PLL mode.
1. In PLLCTL, write CLKMODE = 0 (internal oscillator) or 1 (input clock) to select the type of reference
clock. Write CLKMODE = 0 for internal oscillator. Write CLKMODE = 1 for square wave input clock.
2. In PLLCTL, write PLLENSRC = 0 (enable PLL enable). The bit PLLEN in PLLCTL has no effect unless
you write PLLENSRC = 0.
3. In PLLCTL, write PLLEN = 0 (bypass mode).
4. Wait at least 4 reference clock cycles for the PLLEN mux to change.
5. In PLLCTL, write PLLRST = 1 (assert PLL reset).
6. In PLLCTL, write PLLDIS = 1 (assert PLL disable).
7. In PLLCTL, write PLLPWRDN = 0 (power up the PLL).
8. In PLLCTL, write PLLDIS = 0 (de-assert PLL disable).
9. If necessary, write PREDIV, POSTDIV, and PLLM to set divider and multiplier values.
10. If necessary, write PLLDIV to set PLLDIVn dividers. Note that you must apply the GO operation to
change these dividers to new ratios. See
11. Wait at least 5 miro-seconds for the PLL reset.
12. In PLLCTL, write PLLRST = 0 (de-assert PLL reset).
13. Wait at least 8000 reference clock cycles for the PLL to lock.
14. In PLLCTL, write PLLEN = 1 to (switch from bypass mode to PLL mode).
This section describes the sequence for bypass mode.
1. In PLLCTL, write PLLEN = 0 (bypass mode).
2. Wait at least four reference clock cycles for the PLLEN mux to change.
3. In PLLCTL, write PLLRST = 1 (assert PLL reset).
4. It is not necessary to program PREDIV, PLLM, and POSTDIV; because they have no effect in bypass
mode.
5. If necessary, program PLLDIVn. Note that you must apply the GO operation to change these dividers
to new ratios. See
.
This section describes how to change divider and multiplier values.
The GO operation is required to change the divider ratios of the PLLDIVn registers. Section
discusses the GO operation.
gives the software steps required to
change the divider ratios.
PLL Controllers (PLLCs)
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SPRUFX7 – July 2008