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4.1
Memory Map
SPRUFX7 – July 2008
Memory Mapping
The device memory map is shown in
. The multiple columns represent the memory map of each
of the masters on the chip. The ARM, EDMA, USB, and VPSS are all masters with access to the regions
shown in the table. The table’s memory size column shows the size of the decoded block; it may not show
the physical memory range. There may be replication of the contents within the block (as with the 8K ARM
ROM) or unused address space within the block.
Table 4-1. Memory Map
Start Address
End Address
Size (Bytes)
ARM
EDMA
USB
VPSS
Mem Map
Mem Map
Mem Map
Mem Map
0x0000 0000
0x0000 3FFF
16K
ARM RAM0
(Instruction)
0x0000 4000
0x0000 7FFF
16K
ARM RAM1
Reserved
Reserved
(Instruction)
0x0000 8000
0x0000 FFFF
32K
ARM ROM
(Instruction)
- only 8K used
0x0001 0000
0x0001 3FFF
16K
ARM RAM0 (Data)
ARM RAM0
ARM RAM0
0x0001 4000
0x0001 7FFF
16K
ARM RAM1 (Data)
ARM RAM1
ARM RAM1
0x0001 8000
0x0001 FFFF
32K
ARM ROM (Data)
ARM ROM
ARM ROM
- only 8K used
0x0002 0000
0x000F FFFF
896K
Reserved
0x0010 0000
0x01BB FFFF
26M
0x01BC 0000
0x01BC 0FFF
4K
ARM ETB Mem
0x01BC 1000
0x01BC 17FF
2K
ARM ETB Reg
Reserved
0x01BC 1800
0x01BC 18FF
256
ARM IceCrusher
Reserved
0x01BC 1900
0x01BC FFFF
59136
Reserved
0x01BD 0000
0x01BF FFFF
192K
0x01C0 0000
0x01FF FFFF
4M
CFG Bus
CFG Bus
Reserved
Peripherals
Peripherals
0x0200 0000
0x09FF FFFF
128M
ASYNC EMIF
ASYNC EMIF
(Data)
(Data)
0x0A00 0000
0x11EF FFFF
127M - 16K
0x11F0 0000
0x11F1 FFFF
128K
Reserved
Reserved
0x11F2 0000
0x1FFF FFFF
141M-64K
0x2000 0000
0x2000 7FFF
32K
DDR EMIF Control
DDR EMIF Control
Regs
Regs
0x2000 8000
0x41FF FFFF
544M-32K
Reserved
0x4200 0000
0x49FF FFFF
128M
Reserved
Reserved
0x4A00 0000
0x7FFF FFFF
864M
Reserved
0x8000 0000
0x8FFF FFFF
256M
DDR EMIF
DDR EMIF
DDR EMIF
DDR EMIF
0x9000 0000
0xFFFF FFFF
1792M
Reserved
Reserved
Reserved
Reserved
SPRUFX7 – July 2008
Memory Mapping
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