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Prioritization within each switched central resource (SCR) is selected to be either fixed or dynamic.
Dynamic prioritization is based on an incoming priority signal from each master. On the device, only the
VPSS and EDMA masters actually generate priority values. For all other masters, the value is
programmed in the chip-level MSTRPRI registers. The default priority level for each device bus master is
shown in
. Application software is expected to modify these values to obtain the desired system
performance.
Table 9-2. Default Master Priorities
Master
Default Priority
VPSS
0
(1)
EDMA Ch 0
0
EDMA Ch 1
0
ARM (DMA)
1
ARM (CFG)
1
Reserved
-
Reserved
-
Reserved
-
Reserved
-
USB
4
Reserved
-
Reserved
-
Reserved
-
Reserved
-
(1)
Default value in VPSS PCR register
System Control Module
116
SPRUFX7 – July 2008