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3.7
Tightly Coupled Memory
Tightly Coupled Memory
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The ARM926EJ-Shas a tightly coupled memory interface enabling separate instruction and data TCM to
be interfaced to the ARM. TCMs are meant for storing real-time and performance critical code.
The device supports both instruction TCM (I-TCM) and data TCM (D-TCM). The instruction TCM is located
at 0x0000:0000 to 0x0000:7FFF. The data TCM is located at 0x0001:0000 to 0x0001:7FFF, as shown in
Table 3-3. ITCM/DTCM Memory Map
I-TCM Address
D-TCM Address
Size (Bytes)
Description
0x0000 :0000 - 0x0000 :3FFF
0x0001 :0000 - 0x0001 :3FFF
16K
IRAM0
0x0000 :4000 - 0x0000 :7FFF
0x0001 :4000 - 0x0001 :7FFF
16K
IRAM1
0x0000 :8000 - 0x0000 :BFFF
0x0001 :8000 - 0x0001 :8FFF
16K
ROM
0x0000 :C000 - 0x0000 :FFFF
0x0001 :C000 - 0x000F :FFFF
16K
Reserved
The status of the TCM memory regions can be read from the TCM status register, which is CP15 register
0. The instruction for reading the TCM status is given below:
MRC p15, #0, Rd, c0, c0, #2
; read TCM status register
where Rd is any register where the status data is read into the register.
The format of the data in the TCM register is as shown below:
31
17
16
SBZ/U
DTCM
NP
15
1
0
SBZ/U
ITCM
NP
If the DTCM bit is 0, Data TCM is not present and if the DTCM bit is 1, Data TCM is present. If the ITCM
bit is 0, Instruction TCM is not present and if the ITCM bit is 1, Instruction TCM is present.
Use the ITCM / DTCM region registers to enable ITCM and DTCM.
The instructions for reading and writing to the ITCM and DTCM are shown below:
MRC p15, #0, Rd, c9, c0, #0
; read DTCM region register
MCR p15, #0, Rd, c9, c0, #0
; write DTCM region register
MRC p15, #0, Rd, c9, c0, #1
; read ITCM region register
MCR p15, #0, Rd, c9, c0, #1
; write ITCM region register
Where Rd is any register where the data is read or written into the register.
The format of the data in the TCM register is shown below:
31
16
ADDR
ESS
15
12
11
6
5
2
1
0
ADDR
SBZ/U
SIZE
0
ENB
ESS
NP
ARM Core
26
SPRUFX7 – July 2008