10.4.5 AEMIF Configuration
10.4.5.1 AEMIF Pin Configuration
10.4.5.2 AEMIF Timing Configuration
Default Device Configurations
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Boot modes are further described in
For more information on the AEMIF, see the
TMS320DM335 Digital Media System-on-Chip (DMSoC)
Asynchronous External Memory Interface (EMIF) Reference Guide
)
The input pins AECFG[3:0] determine the AEMIF configuration immediately after reset. Use AECFG[3:0]
to properly configure the pins of the AEMIF. Refer to the section on pin multiplexing in
.
When AEMIF is enabled, the wait state registers are reset to the slowest possible configuration, which is
88 cycles per access (16 cycles of setup, 64 cycles of strobe, and 8 cycles of hold). Thus, with a 24 MHz
clock at MXI/MXO, the AEMIF is configured to run at (6 MHz)/(88) which equals approximately 68 kHz.
Reset
148
SPRUFX7 – July 2008