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3.8
Embedded Trace Support
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Embedded Trace Support
Write 0 to the ENB bit to enable ITCM and DTCM. Write 1 to the ENB bit to enable it. The physical
address of the memory should be set to the ADDRESS field. The SIZE field reflects the size. The size
encoding is given below in
Table 3-4. ITCM/DTCM Size Encoding
Binary Code
Size
0000
0 KB / absent
0001,0010
Reserved
0011
4 KB
0100
8 KB
0101
16 KB
0110
32 KB
0111
64 KB
1000
128 KB
1001
256 KB
1010
512 KB
1011
1 MB
11xx
Reserved
Note:
See
of the Tightly-coupled Memory Interface of the ARM926EJ-S TRM,
downloadable from
for more detailed information.
Use the values 0x00010019 to enable DTCM for the device: 0x00010000 (base address) |
0b0110 << 2 (size) | 1 (enable)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the device also includes the
Embedded Trace Buffer (ETB).
The ETM consists of two parts: the trace port and triggering facilities. The two ETM parts are shown in
Note:
The device trace port is not pinned out. Instead, it is connected to a 4KB Embedded Trace
Buffer. ETB enabled debug tools are required to read/interpret the captured trace data.
Table 3-5. ETM Part Descriptions
ETM Part
Description
Trace Port:
The trace port allows you to debug the processor. The trace port has a protocol that has been
developed to provide a real-time trace capability for processor cores that are deeply embedded in
large ASIC designs. This is beneficial to developers and manufacturers when it is not possible to
determine how the processor core is operating by only observing the pins of the ASIC.
Triggering Facilities:
An extensible ETM specification exists to specify the exact set of trigger resources required for a
particular application. Resources include address and data comparators, counters, and
sequencers.
SPRUFX7 – July 2008
ARM Core
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