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4.1.1 ARM Internal Memories
4.1.2 External Memories
4.1.3 Peripherals
Memory Map
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The ARM has access to the following ARM internal memories:
•
32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow
simultaneous access on any given cycle, if there are separate accesses for code (I-TCM bus) and data
(D-TCM) to the different memory regions.
•
8KB ARM Internal ROM
Note:
By default, ARM access to internal memory is with one wait-state. However, if the ARM clock
frequency is less than or equal to 150 MHz, you may configure ARM access to internal
memory to be zero wait-state. To configure the wait-state use the bit AIM_WAIST in the
Miscellaneous Control register (MISC) in the System Control Module. MISC is described in
The ARM has access to the following external memories:
•
DDR2 / mDDR Synchronous DRAM
•
Asynchronous EMIF/OneNand
•
NAND Flash
•
External host devices
Additionally, the ARM has access to the various common media storage card interfaces.
The ARM and EDMA have access to the registers and memories of the following peripherals (see
•
EDMA Controller
•
Three UARTs
•
I2C (Inter-IC Communication)
•
Three 64-bit timers (each configurable as one 64-bit timer or two 32 bit timers) and one WDT
•
PWM (Pulse Width Modulator)
•
USB (Universal Serial Bus Controller)
•
Two Audio Serial Ports (ASP)
•
Three SPI serial interfaces
•
General-Purpose Input/Output (GPIO)
•
Video Processing Subsystem (VPSS)
•
Asynchronous EMIF (AEMIF) Controller
•
Real Time Out (RTO)
The ARM and EDMA also has access to the following internal peripherals:
•
ETM/ETB
•
ICEcrusher
•
System Module
•
PLL Controllers
•
Power Sleep Controller
•
ARM Interrupt Controller
The ARM and EDMA also has access to the following internal peripherals:
Memory Mapping
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SPRUFX7 – July 2008