![background image](http://html.mh-extra.com/html/texas-instruments/tms320dm335/tms320dm335_user-manual_1097123095.webp)
8.4.2 Fast Interrupt Request Status Register 1 (FIQ1)
www.ti.com
INTC Registers
The fast interrupt request status register 1 (FIQ1) is shown in
and described in
Figure 8-6. Interrupt Status of INT[63:32] (if mapped to FIQ)
31
0
FIQ[63:32]
R/W-1
LEGEND: R/W = Read/Write; n = value at reset
Table 8-4. Interrupt Status of INT[63:32] (if mapped to FIQ) Field Descriptions
Bit
Field
Value
Description
31-0
FIQ[63:32]
Interrupt status of INTx, if mapped to FIQ.
0
Rd: Interrupt occurred.
1
Wr: Acknowledge interrupt.
SPRUFX7 – July 2008
Interrupt Controller
95